{"id":"https://openalex.org/W2055132972","doi":"https://doi.org/10.1109/3dic.2013.6702354","title":"Test-TSV estimation during 3D-IC partitioning","display_name":"Test-TSV estimation during 3D-IC partitioning","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2055132972","doi":"https://doi.org/10.1109/3dic.2013.6702354","mag":"2055132972"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2013.6702354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055630366","display_name":"Shreepad Panth","orcid":"https://orcid.org/0000-0001-6296-8453"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shreepad Panth","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Georgia Institute of Technology, GA, Atlanta","[Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Georgia Institute of Technology, GA, Atlanta","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025604916","display_name":"Kambiz Samadi","orcid":null},"institutions":[{"id":"https://openalex.org/I19268510","display_name":"Qualcomm (United Kingdom)","ror":"https://ror.org/04d3djg48","country_code":"GB","type":"company","lineage":["https://openalex.org/I19268510","https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Kambiz Samadi","raw_affiliation_strings":["Qualcomm Research, San Diego, CA","[Qualcomm Research, San Diego, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Qualcomm Research, San Diego, CA","institution_ids":["https://openalex.org/I4210087596"]},{"raw_affiliation_string":"[Qualcomm Research, San Diego, CA, USA]","institution_ids":["https://openalex.org/I19268510"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Georgia Institute of Technology, GA, Atlanta","[Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Georgia Institute of Technology, GA, Atlanta","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5055630366"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.2364,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6090628,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.72128826379776},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.6795471906661987},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6323138475418091},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.6121348738670349},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.5849117636680603},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.548878014087677},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5480983853340149},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4967558979988098},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.48284631967544556},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.44867444038391113},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.402972012758255},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33738091588020325},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3237806558609009},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3101128041744232},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24290457367897034},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20405954122543335}],"concepts":[{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.72128826379776},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.6795471906661987},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6323138475418091},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.6121348738670349},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.5849117636680603},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.548878014087677},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5480983853340149},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4967558979988098},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.48284631967544556},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.44867444038391113},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.402972012758255},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33738091588020325},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3237806558609009},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3101128041744232},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24290457367897034},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20405954122543335},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2013.6702354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1965451131","https://openalex.org/W2017255835","https://openalex.org/W2048927144","https://openalex.org/W2074730724","https://openalex.org/W2082029044","https://openalex.org/W2090396476","https://openalex.org/W2102270287","https://openalex.org/W2112647513","https://openalex.org/W2116426145","https://openalex.org/W2132155220","https://openalex.org/W2143502515","https://openalex.org/W2151243068","https://openalex.org/W2158277795","https://openalex.org/W2163273848","https://openalex.org/W4245053922","https://openalex.org/W6677637676"],"related_works":["https://openalex.org/W2016970881","https://openalex.org/W2027159884","https://openalex.org/W1990828594","https://openalex.org/W2333804548","https://openalex.org/W2534942874","https://openalex.org/W3093450488","https://openalex.org/W2016589506","https://openalex.org/W2376702355","https://openalex.org/W4385062230","https://openalex.org/W2084347051"],"abstract_inverted_index":{"Three":[0],"dimensional":[1],"integrated":[2],"circuits":[3],"(3D-ICs)":[4],"are":[5,28],"emerging":[6],"as":[7,153],"a":[8,21,66,133,146,169],"viable":[9],"solution":[10],"to":[11,46,49,54,93,100,122,156,159],"the":[12,41,50,62,83,90,95,102,139,157,162],"interconnect":[13],"scaling":[14],"problem.":[15],"During":[16,37],"early":[17],"design":[18,63],"space":[19],"exploration,":[20],"large":[22],"number":[23,42,85,141,164],"of":[24,43,86,138,142,165],"possible":[25],"partitioning":[26],"solutions":[27],"evaluated":[29],"w.r.t.":[30],"performance,":[31],"area,":[32],"through-silicon-via":[33],"(TSV)":[34],"count,":[35,53],"etc.":[36],"this":[38,75,129],"evaluation":[39],"process,":[40],"test-TSVs":[44,87,143],"need":[45],"be":[47,123,151],"added":[48],"total":[51,163],"TSV":[52],"prevent":[55],"unexpected":[56],"area":[57],"overhead":[58],"later":[59],"on":[60],"in":[61,74,125],"flow.":[64],"While":[65],"fixed":[67],"test-TSV":[68,97,103],"count":[69,98],"may":[70],"provide":[71],"sufficient":[72],"guardbanding,":[73],"paper":[76],"we":[77,131],"show":[78],"that":[79],"it":[80],"often":[81],"overestimates":[82],"actual":[84],"required.":[88],"Currently,":[89],"only":[91],"way":[92],"determine":[94],"pareto-optimial":[96],"is":[99,115,119],"sweep":[101],"constraint,":[104],"and":[105,118,135],"repeatedly":[106],"apply":[107],"3D":[108],"test":[109],"architecture":[110],"optimization":[111],"algorithms.":[112],"This":[113,149],"process":[114],"time":[116],"consuming,":[117],"too":[120],"slow":[121],"used":[124,152,167],"automated":[126],"partitioning.":[127],"In":[128],"paper,":[130],"present":[132],"quick":[134],"accurate":[136],"estimation":[137],"pareto-optimal":[140],"required":[144],"for":[145,168],"given":[147,170],"partition.":[148],"can":[150],"an":[154],"input":[155],"partitioner":[158],"quickly":[160],"estimate":[161],"TSVs":[166],"partition,":[171],"reducing":[172],"over-design.":[173]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
