{"id":"https://openalex.org/W4317815260","doi":"https://doi.org/10.1109/wsc57314.2022.10015298","title":"A Generalized Model for Modern Hierarchical Memory System","display_name":"A Generalized Model for Modern Hierarchical Memory System","publication_year":2022,"publication_date":"2022-12-11","ids":{"openalex":"https://openalex.org/W4317815260","doi":"https://doi.org/10.1109/wsc57314.2022.10015298"},"language":"en","primary_location":{"id":"doi:10.1109/wsc57314.2022.10015298","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/wsc57314.2022.10015298","pdf_url":null,"source":{"id":"https://openalex.org/S4363607869","display_name":"2022 Winter Simulation Conference (WSC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Winter Simulation Conference (WSC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101702763","display_name":"Hamed Najafi","orcid":"https://orcid.org/0009-0004-6528-8671"},"institutions":[{"id":"https://openalex.org/I19700959","display_name":"Florida International University","ror":"https://ror.org/02gz6gg07","country_code":"US","type":"education","lineage":["https://openalex.org/I19700959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hamed Najafi","raw_affiliation_strings":["Knight Foundation School of Computing and Information Sciences, Florida International University,Miami,FL,USA,33199"],"affiliations":[{"raw_affiliation_string":"Knight Foundation School of Computing and Information Sciences, Florida International University,Miami,FL,USA,33199","institution_ids":["https://openalex.org/I19700959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083193232","display_name":"Jason Liu","orcid":"https://orcid.org/0000-0001-8222-4013"},"institutions":[{"id":"https://openalex.org/I19700959","display_name":"Florida International University","ror":"https://ror.org/02gz6gg07","country_code":"US","type":"education","lineage":["https://openalex.org/I19700959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Liu","raw_affiliation_strings":["Knight Foundation School of Computing and Information Sciences, Florida International University,Miami,FL,USA,33199"],"affiliations":[{"raw_affiliation_string":"Knight Foundation School of Computing and Information Sciences, Florida International University,Miami,FL,USA,33199","institution_ids":["https://openalex.org/I19700959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071271406","display_name":"Xiaoyang Lu","orcid":"https://orcid.org/0009-0005-9481-7234"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaoyang Lu","raw_affiliation_strings":["Illinois Institute of Technology,Department of Computer Science,Chicago,IL,USA,60616"],"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology,Department of Computer Science,Chicago,IL,USA,60616","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057665558","display_name":"Xian\u2010He Sun","orcid":"https://orcid.org/0000-0002-1093-0792"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xian-He Sun","raw_affiliation_strings":["Illinois Institute of Technology,Department of Computer Science,Chicago,IL,USA,60616"],"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology,Department of Computer Science,Chicago,IL,USA,60616","institution_ids":["https://openalex.org/I180949307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101702763"],"corresponding_institution_ids":["https://openalex.org/I19700959"],"apc_list":null,"apc_paid":null,"fwci":0.6426,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61779575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"2178","last_page":"2188"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8214056491851807},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.7216916680335999},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6785855293273926},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.662561297416687},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.6554768681526184},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5940515995025635},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5741226673126221},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5384058952331543},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5310932397842407},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4878842830657959},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.4694482982158661},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4451688826084137},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4386940896511078},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.43371817469596863},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4312973916530609},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4226575493812561},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4213339686393738},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41485556960105896},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3494945764541626},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16750958561897278}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8214056491851807},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.7216916680335999},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6785855293273926},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.662561297416687},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.6554768681526184},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5940515995025635},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5741226673126221},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5384058952331543},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5310932397842407},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4878842830657959},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.4694482982158661},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4451688826084137},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4386940896511078},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.43371817469596863},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4312973916530609},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4226575493812561},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4213339686393738},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41485556960105896},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3494945764541626},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16750958561897278},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/wsc57314.2022.10015298","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/wsc57314.2022.10015298","pdf_url":null,"source":{"id":"https://openalex.org/S4363607869","display_name":"2022 Winter Simulation Conference (WSC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Winter Simulation Conference (WSC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3719010016","display_name":null,"funder_award_id":"CCF-2008000,CCF-2008907","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1978085294","https://openalex.org/W1997678386","https://openalex.org/W2126274747","https://openalex.org/W2624172078","https://openalex.org/W2804240217","https://openalex.org/W2942006733","https://openalex.org/W3128413462","https://openalex.org/W4253086812","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W3108993429","https://openalex.org/W2782503170","https://openalex.org/W4317815260","https://openalex.org/W4321458411","https://openalex.org/W1575240748","https://openalex.org/W2047684617","https://openalex.org/W1975698617","https://openalex.org/W2168550483","https://openalex.org/W2145484885","https://openalex.org/W2096506606"],"abstract_inverted_index":{"Memory":[0,15],"system":[1,27,66,106],"is":[2,19],"critical":[3],"to":[4,70,73],"architecture":[5,92],"design":[6],"which":[7],"can":[8],"significantly":[9],"impact":[10],"application":[11],"performance.":[12],"Concurrent":[13],"Average":[14],"Access":[16],"Time":[17],"(C-AMAT)":[18],"a":[20,30],"model":[21,101],"for":[22,55],"analyzing":[23],"and":[24,53,64,102],"optimizing":[25],"memory":[26,35,40,58,62,91,105],"performance":[28,107],"using":[29,111],"recursive":[31],"definition":[32],"of":[33,79],"the":[34,39,50,77,90,99,104,112],"access":[36],"latency":[37],"along":[38],"hierarchy.":[41],"The":[42],"original":[43,113],"C-AMAT":[44,72,114],"model,":[45],"however,":[46],"does":[47],"not":[48],"provide":[49],"necessary":[51],"granularity":[52],"flexibility":[54],"handling":[56],"modern":[57],"architectures":[59],"with":[60,108],"heterogeneous":[61],"technologies":[63],"diverse":[65],"topology.":[67],"We":[68],"propose":[69],"augment":[71],"take":[74],"into":[75],"consideration":[76],"idiosyncrasies":[78],"individual":[80],"cache/memory":[81],"components":[82],"as":[83,85],"well":[84],"their":[86],"topological":[87],"arrangement":[88],"in":[89],"design.":[93],"Through":[94],"trace-based":[95],"simulation,":[96],"we":[97],"validate":[98],"augmented":[100],"examine":[103],"insight":[109],"unavailable":[110],"model.":[115]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}