{"id":"https://openalex.org/W4235725903","doi":"https://doi.org/10.1109/wsc.2009.5429289","title":"On the scalability and dynamic load balancing of parallel Verilog simulations","display_name":"On the scalability and dynamic load balancing of parallel Verilog simulations","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W4235725903","doi":"https://doi.org/10.1109/wsc.2009.5429289"},"language":"en","primary_location":{"id":"doi:10.1109/wsc.2009.5429289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/wsc.2009.5429289","pdf_url":null,"source":{"id":"https://openalex.org/S4363608998","display_name":"Proceedings of the 2009 Winter Simulation Conference (WSC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 Winter Simulation Conference (WSC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038522665","display_name":"Sina Meraji","orcid":null},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Sina Meraji","raw_affiliation_strings":["School of Computer Science, McGill University, Montreal, QUE, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, McGill University, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100441535","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0001-9405-447X"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["School of Computer Science, McGill University, Montreal, QUE, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, McGill University, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045603103","display_name":"Carl Tropper","orcid":null},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Carl Tropper","raw_affiliation_strings":["School of Computer Science, McGill University, Montreal, QUE, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, McGill University, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I5023651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0148,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.79504505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1366","last_page":"1374"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8375333547592163},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7544006109237671},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.678207516670227},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.585442841053009},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5280005931854248},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45407235622406006},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.42166927456855774},{"id":"https://openalex.org/keywords/viterbi-decoder","display_name":"Viterbi decoder","score":0.41873103380203247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28891146183013916},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.2527334988117218},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12502533197402954},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10579550266265869},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07957974076271057},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0726148784160614}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8375333547592163},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7544006109237671},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.678207516670227},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.585442841053009},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5280005931854248},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45407235622406006},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.42166927456855774},{"id":"https://openalex.org/C117379686","wikidata":"https://www.wikidata.org/wiki/Q6996459","display_name":"Viterbi decoder","level":3,"score":0.41873103380203247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28891146183013916},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.2527334988117218},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12502533197402954},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10579550266265869},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07957974076271057},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0726148784160614},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/wsc.2009.5429289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/wsc.2009.5429289","pdf_url":null,"source":{"id":"https://openalex.org/S4363608998","display_name":"Proceedings of the 2009 Winter Simulation Conference (WSC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 Winter Simulation Conference (WSC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W120905807","https://openalex.org/W1514439880","https://openalex.org/W1517105504","https://openalex.org/W2025516544","https://openalex.org/W2065589938","https://openalex.org/W2140995526","https://openalex.org/W2154620955","https://openalex.org/W2166959082","https://openalex.org/W2296636214","https://openalex.org/W2588783721","https://openalex.org/W2972789347","https://openalex.org/W3004441525","https://openalex.org/W4250192995","https://openalex.org/W4254131023","https://openalex.org/W6733731328"],"related_works":["https://openalex.org/W2136295006","https://openalex.org/W2165480138","https://openalex.org/W2107240870","https://openalex.org/W2107517480","https://openalex.org/W4210326786","https://openalex.org/W4231001357","https://openalex.org/W2131024837","https://openalex.org/W2539742022","https://openalex.org/W2063218591","https://openalex.org/W2117342402"],"abstract_inverted_index":{"As":[0,42],"a":[1,34,67,128],"consequence":[2],"of":[3,8,33,48,58,130],"Moore's":[4],"law,":[5],"the":[6,18,22,31,56,90,93,112],"size":[7],"integrated":[9],"circuits":[10,60,85],"has":[11,45],"grown":[12],"extensively,":[13],"resulting":[14],"in":[15,21,76,135],"simulation":[16],"becoming":[17],"major":[19],"bottleneck":[20],"circuit":[23],"design":[24],"process.":[25],"In":[26],"this":[27],"paper,":[28],"we":[29],"examine":[30],"performance":[32],"parallel":[35,77],"Verilog":[36,70,80],"simulator":[37],"on":[38,108],"large,":[39],"real":[40],"designs.":[41],"previous":[43],"work":[44],"made":[46],"use":[47,57,140],"either":[49],"relatively":[50],"small":[51],"benchmarks":[52],"or":[53],"synthetic":[54],"circuits,":[55],"these":[59],"is":[61,123],"far":[62],"more":[63],"realistic.":[64],"We":[65,82,102],"develop":[66],"parser":[68],"for":[69,111,141],"files":[71],"enabling":[72],"us":[73],"to":[74,137],"simulate":[75],"all":[78],"synthesizable":[79],"circuits.":[81,101,143],"utilize":[83],"four":[84],"as":[86],"our":[87],"test":[88],"benches;":[89],"LEON":[91],"Processor,":[92],"OpenSparc":[94],"T2":[95],"processor":[96],"and":[97,132],"two":[98],"Viterbi":[99,113],"decoder":[100,114],"observed":[103],"4,000,000":[104],"events":[105],"per":[106],"second":[107],"32":[109],"processors":[110],"with":[115],"800k":[116],"gates.":[117],"A":[118],"dynamic":[119],"load":[120],"balancing":[121],"approach":[122],"also":[124],"developed":[125],"which":[126],"uses":[127],"combination":[129],"centralized":[131],"distributed":[133],"control":[134],"order":[136],"accommodate":[138],"its":[139],"large":[142]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
