{"id":"https://openalex.org/W2132411677","doi":"https://doi.org/10.1109/weah.2009.4925667","title":"Self-adaptive evolution of complex logic circuits","display_name":"Self-adaptive evolution of complex logic circuits","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2132411677","doi":"https://doi.org/10.1109/weah.2009.4925667","mag":"2132411677"},"language":"en","primary_location":{"id":"doi:10.1109/weah.2009.4925667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/weah.2009.4925667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Workshop on Evolvable and Adaptive Hardware","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111910513","display_name":"Xiaoxuan She","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaoxuan She","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan UNIVERSITY, China","State Key Laboratory of ASIC and System, Fudan University,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan UNIVERSITY, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan UNIVERSITY, China","State Key Laboratory of ASIC and System, Fudan University,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan UNIVERSITY, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111910513"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.8724,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.80910885,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"47","last_page":"53"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10878","display_name":"CRISPR and Genetic Engineering","score":0.9262999892234802,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/evolvable-hardware","display_name":"Evolvable hardware","score":0.9253699779510498},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7376644611358643},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6916667819023132},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6120153069496155},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5464467406272888},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49901556968688965},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4935187101364136},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.48146000504493713},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4607921540737152},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44180989265441895},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4197908043861389},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41789841651916504},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4106995165348053},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32928916811943054},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31713438034057617},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19998231530189514},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14093399047851562}],"concepts":[{"id":"https://openalex.org/C2776243922","wikidata":"https://www.wikidata.org/wiki/Q5418727","display_name":"Evolvable hardware","level":3,"score":0.9253699779510498},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7376644611358643},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6916667819023132},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6120153069496155},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5464467406272888},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49901556968688965},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4935187101364136},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.48146000504493713},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4607921540737152},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44180989265441895},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4197908043861389},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41789841651916504},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4106995165348053},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32928916811943054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31713438034057617},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19998231530189514},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14093399047851562},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/weah.2009.4925667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/weah.2009.4925667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Workshop on Evolvable and Adaptive Hardware","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1494373562","https://openalex.org/W2036195111","https://openalex.org/W2052573747","https://openalex.org/W2096250182","https://openalex.org/W2099179746","https://openalex.org/W2111764974","https://openalex.org/W2122886313","https://openalex.org/W2126278702","https://openalex.org/W2136827374","https://openalex.org/W2136931103","https://openalex.org/W2138371171","https://openalex.org/W2159398783","https://openalex.org/W2160213673","https://openalex.org/W2160301941","https://openalex.org/W2235047952"],"related_works":["https://openalex.org/W1939541994","https://openalex.org/W818963952","https://openalex.org/W2499931839","https://openalex.org/W2110968362","https://openalex.org/W4390345338","https://openalex.org/W4238178324","https://openalex.org/W2169337913","https://openalex.org/W2071237164","https://openalex.org/W1702800398","https://openalex.org/W2356822490"],"abstract_inverted_index":{"Evolvable":[0],"hardware":[1,6,48,148],"(EHW)":[2],"refers":[3],"to":[4,27,153],"self-reconfiguration":[5],"design,":[7],"where":[8],"the":[9,13,21,35,38,59,79,93,97,105,117,136,146],"configuration":[10],"is":[11,31],"under":[12],"control":[14],"of":[15,20,37,61,82,99,104,107,119,135,143],"an":[16],"evolution":[17,60,98,118],"algorithm.":[18],"One":[19],"main":[22],"difficulties":[23],"in":[24,102,131],"using":[25],"EHW":[26,68,124],"solve":[28],"real-world":[29],"problems":[30],"scalability,":[32],"which":[33,57],"limits":[34],"size":[36],"circuit":[39,129],"that":[40,92],"may":[41],"be":[42],"evolved.":[43],"This":[44],"paper":[45],"outlines":[46],"evolvable":[47,147],"based":[49],"on":[50],"a":[51,127,132,144,150],"2-LUT":[52],"(2-input":[53],"lookup":[54],"table)":[55],"array,":[56],"allows":[58],"large":[62,120,140,155],"circuits":[63,76,101],"via":[64],"decomposition.":[65],"The":[66,88,122],"proposed":[67,94,123],"has":[69],"been":[70],"tested":[71],"with":[72],"multipliers":[73],"and":[74,110,115,139],"logic":[75,100],"taken":[77],"from":[78],"Microelectronics":[80],"Centre":[81],"North":[83],"Carolina":[84],"(MCNC)":[85],"benchmark":[86],"library.":[87],"experimental":[89],"results":[90],"demonstrate":[91],"scheme":[95],"improves":[96],"terms":[103],"number":[106],"generations,":[108],"area":[109],"delay,":[111],"reduces":[112],"computational":[113],"time":[114],"enables":[116],"circuits.":[121,156],"automatically":[125],"generates":[126],"complete":[128],"netlist":[130],"SDRAM.":[133],"Because":[134],"low":[137],"cost":[138],"data":[141],"storage":[142],"SDRAM,":[145],"provides":[149],"good":[151],"platform":[152],"evolve":[154]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}