{"id":"https://openalex.org/W4253567283","doi":"https://doi.org/10.1109/waccpd.2016.007","title":"A Modern Memory Management System for OpenMP","display_name":"A Modern Memory Management System for OpenMP","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W4253567283","doi":"https://doi.org/10.1109/waccpd.2016.007"},"language":"en","primary_location":{"id":"doi:10.1109/waccpd.2016.007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/waccpd.2016.007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Third Workshop on Accelerator Programming Using Directives (WACCPD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041290212","display_name":"Jason Sewall","orcid":"https://orcid.org/0000-0001-9482-3558"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. D. Sewall","raw_affiliation_strings":["Intel Corporation, Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, California","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084262733","display_name":"S. J. Pennycook","orcid":"https://orcid.org/0000-0003-0237-3823"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. J. Pennycook","raw_affiliation_strings":["Intel Corporation, Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, California","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034033442","display_name":"A. Duran","orcid":"https://orcid.org/0000-0001-9900-1975"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Duran","raw_affiliation_strings":["Intel Corporation, Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, California","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014177260","display_name":"Xinyi Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"X. Tian","raw_affiliation_strings":["Intel Corporation, Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, California","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004013325","display_name":"R. Narayanaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Narayanaswamy","raw_affiliation_strings":["Intel Corporation, Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, California","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"74","issue":null,"first_page":"25","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12127","display_name":"Software System Performance and Reliability","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.87496018409729},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.638903021812439},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6073980331420898},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5948032140731812},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5840346217155457},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5706664323806763},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.555152416229248},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5520638227462769},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.537566065788269},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.51645827293396},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4597196578979492},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4525753855705261},{"id":"https://openalex.org/keywords/high-memory","display_name":"High memory","score":0.43820473551750183},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.4284508228302002},{"id":"https://openalex.org/keywords/auxiliary-memory","display_name":"Auxiliary memory","score":0.4257577061653137},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.4127606153488159},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.3863729238510132},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2863510251045227}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.87496018409729},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.638903021812439},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6073980331420898},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5948032140731812},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5840346217155457},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5706664323806763},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.555152416229248},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5520638227462769},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.537566065788269},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.51645827293396},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4597196578979492},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4525753855705261},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.43820473551750183},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.4284508228302002},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.4257577061653137},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.4127606153488159},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.3863729238510132},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2863510251045227},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/waccpd.2016.007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/waccpd.2016.007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Third Workshop on Accelerator Programming Using Directives (WACCPD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W348433680","https://openalex.org/W1973858832","https://openalex.org/W1984222112","https://openalex.org/W2038509324","https://openalex.org/W2078794610","https://openalex.org/W2083790008","https://openalex.org/W2086329118","https://openalex.org/W2090809553","https://openalex.org/W2095881341","https://openalex.org/W2128274900","https://openalex.org/W2134484933","https://openalex.org/W2149590159","https://openalex.org/W2163270257","https://openalex.org/W2340076492","https://openalex.org/W2471077310","https://openalex.org/W2473693139","https://openalex.org/W2505067803","https://openalex.org/W2529487057","https://openalex.org/W2725179571","https://openalex.org/W3138798301","https://openalex.org/W4231462625","https://openalex.org/W4238826965","https://openalex.org/W4255817501","https://openalex.org/W6720284283","https://openalex.org/W6721034629","https://openalex.org/W6724974704","https://openalex.org/W6728321799"],"related_works":["https://openalex.org/W4248614727","https://openalex.org/W2296275612","https://openalex.org/W2753615087","https://openalex.org/W3048967625","https://openalex.org/W2044064773","https://openalex.org/W1979982061","https://openalex.org/W2140386982","https://openalex.org/W2526409495","https://openalex.org/W3035532779","https://openalex.org/W1527643973"],"abstract_inverted_index":{"Modern":[0],"computers":[1],"with":[2,100],"multi-/many-core":[3],"processors":[4],"and":[5,10,23,34,73,88,96],"accelerators":[6],"feature":[7],"a":[8,71],"sophisticated":[9],"deep":[11],"memory":[12,22,68,83],"hierarchy,":[13],"potentially":[14],"including":[15],"distinct":[16],"main":[17],"memory,":[18,20],"high-bandwidth":[19],"texture":[21],"scratchpad":[24],"memory.":[25],"The":[26],"performance":[27],"characteristics":[28,81,90],"of":[29,40,50,58,82,91],"these":[30],"memories":[31],"are":[32],"varied,":[33],"studies":[35],"have":[36],"demonstrated":[37],"the":[38,51,56,80,89],"importance":[39],"using":[41],"them":[42],"effectively.In":[43],"this":[44],"paper,":[45],"we":[46],"propose":[47],"an":[48],"extension":[49],"OpenMP":[52,102],"API":[53],"to":[54,60,65],"address":[55],"needs":[57],"programmers":[59],"efficiently":[61],"optimize":[62],"their":[63],"applications":[64],"use":[66],"new":[67],"technologies":[69],"in":[70],"platform-agnostic":[72],"portable":[74],"fashion.":[75],"Our":[76],"proposal":[77],"separately":[78],"exposes":[79],"resources":[84],"(such":[85,93],"as":[86,94],"kind)":[87],"allocations":[92],"alignment),":[95],"is":[97],"fully":[98],"compatible":[99],"existing":[101],"constructs.":[103]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}