{"id":"https://openalex.org/W7165177915","doi":"https://doi.org/10.1109/vts69484.2026.11563337","title":"Innovative Practices Session: Efficient Multi-Die Test Architecture &amp; Repair Methods","display_name":"Innovative Practices Session: Efficient Multi-Die Test Architecture &amp; Repair Methods","publication_year":2026,"publication_date":"2026-04-27","ids":{"openalex":"https://openalex.org/W7165177915","doi":"https://doi.org/10.1109/vts69484.2026.11563337"},"language":null,"primary_location":{"id":"doi:10.1109/vts69484.2026.11563337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts69484.2026.11563337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 44th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085944984","display_name":"T.J. Chakraborty","orcid":"https://orcid.org/0000-0001-9383-9603"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]},{"id":"https://openalex.org/I75636454","display_name":"Renesas Electronics (United States)","ror":"https://ror.org/014775w70","country_code":"US","type":"company","lineage":["https://openalex.org/I4210153176","https://openalex.org/I75636454"]}],"countries":["JP","US"],"is_corresponding":false,"raw_author_name":"Tapan J Chakraborty","raw_affiliation_strings":["Renesas Electronics,America"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Electronics,America","institution_ids":["https://openalex.org/I75636454","https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011718134","display_name":"R. Pendurkar","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajesh Pendurkar","raw_affiliation_strings":["Cadence Design Systems"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041100073","display_name":"Anshuman Chandra","orcid":"https://orcid.org/0000-0002-2686-3918"},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Anshuman Chandra","raw_affiliation_strings":["Siemens EDA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens EDA","institution_ids":["https://openalex.org/I1325886976"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044465911","display_name":"Jennifer Dworak","orcid":null},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jennifer Dworak","raw_affiliation_strings":["Southern Methodist University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southern Methodist University","institution_ids":["https://openalex.org/I178169726"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102622960","display_name":"Moiz Khan","orcid":null},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Moiz Khan","raw_affiliation_strings":["Siemens EDA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens EDA","institution_ids":["https://openalex.org/I1325886976"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5138931563","display_name":"Vinay Kumar Kotha","orcid":null},"institutions":[{"id":"https://openalex.org/I135428043","display_name":"Cisco Systems (United States)","ror":"https://ror.org/03yt1ez60","country_code":"US","type":"company","lineage":["https://openalex.org/I135428043"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinay Kumar Kotha","raw_affiliation_strings":["CISCO Systems"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CISCO Systems","institution_ids":["https://openalex.org/I135428043"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.952714,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.2727000117301941,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.2727000117301941,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.03420000150799751,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.03139999881386757,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.487199991941452},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.3846000134944916},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.305400013923645},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.2935999929904938},{"id":"https://openalex.org/keywords/systems-architecture","display_name":"Systems architecture","score":0.2849999964237213}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5378000140190125},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.487199991941452},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3846000134944916},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34689998626708984},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3467000126838684},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.34619998931884766},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.305400013923645},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2935999929904938},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.2888999879360199},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.2849999964237213},{"id":"https://openalex.org/C25343380","wikidata":"https://www.wikidata.org/wiki/Q277521","display_name":"Relation (database)","level":2,"score":0.2768000066280365},{"id":"https://openalex.org/C7166840","wikidata":"https://www.wikidata.org/wiki/Q1199682","display_name":"System testing","level":2,"score":0.2549999952316284},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2524999976158142},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts69484.2026.11563337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts69484.2026.11563337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 44th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.48260605335235596}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-19T15:51:49.773706","created_date":"2026-06-19T00:00:00"}
