{"id":"https://openalex.org/W4282965532","doi":"https://doi.org/10.1109/vts52500.2021.9794232","title":"Fast Test Generation for Structurally Similar Circuits","display_name":"Fast Test Generation for Structurally Similar Circuits","publication_year":2022,"publication_date":"2022-04-25","ids":{"openalex":"https://openalex.org/W4282965532","doi":"https://doi.org/10.1109/vts52500.2021.9794232"},"language":"en","primary_location":{"id":"doi:10.1109/vts52500.2021.9794232","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts52500.2021.9794232","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE 40th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059667914","display_name":"Jerin Joe","orcid":"https://orcid.org/0000-0002-6738-2491"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jerin Joe","raw_affiliation_strings":["Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA","School of Electrical & Computer Engg., Purdue University, W. Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"School of Electrical & Computer Engg., Purdue University, W. Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075158519","display_name":"Nilanjan Mukherjee","orcid":"https://orcid.org/0000-0001-6689-7525"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nilanjan Mukherjee","raw_affiliation_strings":["Siemens Digital Industries Software,Wilsonville,OR,USA","Siemens Digital Industries Software, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Digital Industries Software,Wilsonville,OR,USA","institution_ids":["https://openalex.org/I4210137693"]},{"raw_affiliation_string":"Siemens Digital Industries Software, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210137693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032651920","display_name":"Irith Pomeranz","orcid":"https://orcid.org/0000-0002-5491-7282"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Irith Pomeranz","raw_affiliation_strings":["Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA","School of Electrical & Computer Engg., Purdue University, W. Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"School of Electrical & Computer Engg., Purdue University, W. Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080960636","display_name":"Janusz Rajski","orcid":"https://orcid.org/0000-0003-2124-447X"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Janusz Rajski","raw_affiliation_strings":["Siemens Digital Industries Software,Wilsonville,OR,USA","Siemens Digital Industries Software, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Digital Industries Software,Wilsonville,OR,USA","institution_ids":["https://openalex.org/I4210137693"]},{"raw_affiliation_string":"Siemens Digital Industries Software, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210137693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7915777564048767},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6789502501487732},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6497008204460144},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5978507399559021},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5895739793777466},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5685559511184692},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.563590943813324},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.5460137128829956},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5314955115318298},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5166573524475098},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4848807752132416},{"id":"https://openalex.org/keywords/similarity","display_name":"Similarity (geometry)","score":0.48080936074256897},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4551711678504944},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36633312702178955},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.260198712348938},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24704799056053162},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17312663793563843},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1101439893245697}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7915777564048767},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6789502501487732},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6497008204460144},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5978507399559021},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5895739793777466},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5685559511184692},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.563590943813324},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.5460137128829956},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5314955115318298},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5166573524475098},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4848807752132416},{"id":"https://openalex.org/C103278499","wikidata":"https://www.wikidata.org/wiki/Q254465","display_name":"Similarity (geometry)","level":3,"score":0.48080936074256897},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4551711678504944},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36633312702178955},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.260198712348938},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24704799056053162},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17312663793563843},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1101439893245697},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts52500.2021.9794232","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts52500.2021.9794232","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE 40th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W12081373","https://openalex.org/W1969318341","https://openalex.org/W1988584325","https://openalex.org/W2010444555","https://openalex.org/W2067436859","https://openalex.org/W2071868930","https://openalex.org/W2087656024","https://openalex.org/W2090308255","https://openalex.org/W2109092163","https://openalex.org/W2114494344","https://openalex.org/W2126708646","https://openalex.org/W2130494464","https://openalex.org/W2137589342","https://openalex.org/W2152321821","https://openalex.org/W2155220566","https://openalex.org/W2162256736","https://openalex.org/W2416637375","https://openalex.org/W2958559473","https://openalex.org/W2980396945","https://openalex.org/W3036878327","https://openalex.org/W4212966386","https://openalex.org/W4230124513","https://openalex.org/W4237712334","https://openalex.org/W4240472175","https://openalex.org/W6652974341"],"related_works":["https://openalex.org/W2140497172","https://openalex.org/W4282965532","https://openalex.org/W2150032667","https://openalex.org/W169796002","https://openalex.org/W1843392114","https://openalex.org/W2182071393","https://openalex.org/W2386366670","https://openalex.org/W2533825491","https://openalex.org/W2130108605","https://openalex.org/W1524255947"],"abstract_inverted_index":{"This":[0,76],"paper":[1,56,109],"describes":[2],"a":[3,63,67,71,81,88,112,121],"fast":[4],"test":[5,68,82,89,101,134,139,164],"generation":[6,102,165],"process":[7,105,166],"for":[8,70,85,91,132,141,167],"digital":[9],"circuits":[10,25,34,42,47],"that":[11,26,35],"exhibit":[12],"extensive":[13],"structural":[14,19,113],"similarity.":[15],"The":[16,52,104,128,143],"property":[17],"of":[18,54,62,115,152],"similarity":[20],"can":[21],"be":[22],"seen":[23],"in":[24,107,157],"are":[27,36],"subjected":[28,43],"to":[29,44,58,119],"engineering":[30],"change":[31],"order":[32],"(ECO),":[33],"modified":[37],"during":[38],"place":[39],"and":[40,46,117,126],"route,":[41],"retiming,":[45],"with":[48,111,160],"multiple":[49],"similar":[50,73],"cores.":[51],"goal":[53],"the":[55,60,99,108,162],"is":[57,77,130],"determine":[59],"testability":[61],"circuit":[64,74],"(circuit2)":[65],"given":[66],"set":[69,83,90],"structurally":[72],"(circuit1).":[75],"achieved":[78],"by":[79],"transforming":[80,133],"generated":[84],"circuit1":[86,116,137],"into":[87,138],"circuit2":[92,118],"as":[93,95],"efficiently":[94],"possible,":[96],"without":[97],"repeating":[98],"entire":[100,163],"process.":[103],"described":[106],"starts":[110],"analysis":[114],"obtain":[120],"mapping":[122,129],"between":[123],"their":[124],"inputs":[125],"outputs.":[127],"used":[131],"patterns":[135,140],"from":[136],"circuit2.":[142,168],"experiments":[144],"conducted":[145],"on":[146],"industrial":[147],"designs":[148],"show":[149],"an":[150],"average":[151],"more":[153],"than":[154],"10-fold":[155],"reduction":[156],"runtime,":[158],"compared":[159],"running":[161]},"counts_by_year":[{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
