{"id":"https://openalex.org/W3033396382","doi":"https://doi.org/10.1109/vts48691.2020.9107627","title":"Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits","display_name":"Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3033396382","doi":"https://doi.org/10.1109/vts48691.2020.9107627","mag":"3033396382"},"language":"en","primary_location":{"id":"doi:10.1109/vts48691.2020.9107627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts48691.2020.9107627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 38th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046362822","display_name":"Brett Sparkman","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brett Sparkman","raw_affiliation_strings":["Electrical Engineering, University of Arkansas, Fayetteville, USA"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering, University of Arkansas, Fayetteville, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037749034","display_name":"Scott C. Smith","orcid":"https://orcid.org/0000-0001-9863-6637"},"institutions":[{"id":"https://openalex.org/I181414168","display_name":"Texas A&M University \u2013 Kingsville","ror":"https://ror.org/05abs3w97","country_code":"US","type":"education","lineage":["https://openalex.org/I181414168"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Scott C. Smith","raw_affiliation_strings":["Electrical Engineering and Computer Science, Texas A&M University-Kingsville, Kingsville, USA"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science, Texas A&M University-Kingsville, Kingsville, USA","institution_ids":["https://openalex.org/I181414168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101644887","display_name":"Jia Di","orcid":"https://orcid.org/0000-0001-7718-0220"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Di","raw_affiliation_strings":["Computer Science and Computer Engineering, University of Arkansas, Fayetteville, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Computer Engineering, University of Arkansas, Fayetteville, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5046362822"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":0.9241,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.71341463,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7890186309814453},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7476517558097839},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7065439224243164},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6299575567245483},{"id":"https://openalex.org/keywords/null","display_name":"Null (SQL)","score":0.5882251858711243},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5387389063835144},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5036377310752869},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49044153094291687},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.44815361499786377},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44303980469703674},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.43777045607566833},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.43080833554267883},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3691633939743042},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34145253896713257},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28597038984298706},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2696138024330139},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16458308696746826},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10273945331573486},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.10016384720802307},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0864507257938385},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.0857870876789093},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.07658585906028748},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.07265540957450867},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06897315382957458}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7890186309814453},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7476517558097839},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7065439224243164},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6299575567245483},{"id":"https://openalex.org/C203763787","wikidata":"https://www.wikidata.org/wiki/Q371029","display_name":"Null (SQL)","level":2,"score":0.5882251858711243},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5387389063835144},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5036377310752869},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49044153094291687},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.44815361499786377},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44303980469703674},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.43777045607566833},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.43080833554267883},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3691633939743042},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34145253896713257},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28597038984298706},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2696138024330139},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16458308696746826},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10273945331573486},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.10016384720802307},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0864507257938385},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0857870876789093},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.07658585906028748},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.07265540957450867},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06897315382957458},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts48691.2020.9107627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts48691.2020.9107627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 38th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1584355183","https://openalex.org/W2081240624","https://openalex.org/W2083950284","https://openalex.org/W2102327308","https://openalex.org/W2117299791","https://openalex.org/W2146381271","https://openalex.org/W2500757389","https://openalex.org/W2508013019"],"related_works":["https://openalex.org/W2358223609","https://openalex.org/W2157212570","https://openalex.org/W2134454856","https://openalex.org/W2543176856","https://openalex.org/W4245485844","https://openalex.org/W2006457427","https://openalex.org/W1969142133","https://openalex.org/W1679970298","https://openalex.org/W2140497172","https://openalex.org/W2166402441"],"abstract_inverted_index":{"While":[0],"a":[1,19],"number":[2],"of":[3],"methods":[4],"exist":[5],"for":[6,24],"asynchronous":[7,30],"circuit":[8],"synthesis,":[9],"there":[10],"are":[11],"limited":[12],"applicable":[13],"test":[14,50],"methodologies.":[15],"This":[16],"paper":[17],"presents":[18],"Built-In":[20],"Self-Test":[21],"(BIST)":[22],"method":[23],"Multi-Threshold":[25],"NULL":[26],"Convention":[27],"Logic":[28],"(MTNCL)":[29],"circuits,":[31],"which":[32],"utilizes":[33],"standard":[34],"synchronous":[35],"tools,":[36],"and":[37,49],"is":[38],"automated":[39],"to":[40],"achieve":[41],"maximum":[42],"fault":[43],"coverage":[44],"while":[45],"minimizing":[46],"area":[47],"overhead":[48],"time.":[51]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}