{"id":"https://openalex.org/W3033500180","doi":"https://doi.org/10.1109/vts48691.2020.9107567","title":"Internal I/O Testing: Definition and a Solution","display_name":"Internal I/O Testing: Definition and a Solution","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3033500180","doi":"https://doi.org/10.1109/vts48691.2020.9107567","mag":"3033500180"},"language":"en","primary_location":{"id":"doi:10.1109/vts48691.2020.9107567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts48691.2020.9107567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 38th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102184443","display_name":"Sreejit Chakravarty","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Sreejit Chakravarty","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101754630","display_name":"Fei Su","orcid":"https://orcid.org/0000-0002-3536-8126"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Fei Su","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079045531","display_name":"Indira A Gohad","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Indira A Gohad","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001315258","display_name":"Sudheer V Bandana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sudheer V Bandana","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069885547","display_name":"B S Adithya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"B S Adithya","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108226449","display_name":"Wei-Ming Lim","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wei-Ming Lim","raw_affiliation_strings":["Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5102184443"],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":0.2055,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.49803916,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8796679973602295},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.5908225178718567},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.5906800627708435},{"id":"https://openalex.org/keywords/obstacle","display_name":"Obstacle","score":0.5882484912872314},{"id":"https://openalex.org/keywords/conductor","display_name":"Conductor","score":0.5758100152015686},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5028244853019714},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4525746703147888},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44322171807289124},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3553153872489929},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17271745204925537},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.11877942085266113},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11495354771614075},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06439325213432312}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8796679973602295},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.5908225178718567},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.5906800627708435},{"id":"https://openalex.org/C2776650193","wikidata":"https://www.wikidata.org/wiki/Q264661","display_name":"Obstacle","level":2,"score":0.5882484912872314},{"id":"https://openalex.org/C34800285","wikidata":"https://www.wikidata.org/wiki/Q5159395","display_name":"Conductor","level":2,"score":0.5758100152015686},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5028244853019714},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4525746703147888},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44322171807289124},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3553153872489929},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17271745204925537},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.11877942085266113},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11495354771614075},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06439325213432312},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts48691.2020.9107567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts48691.2020.9107567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 38th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2042667731","https://openalex.org/W2108528814","https://openalex.org/W2114081084"],"related_works":["https://openalex.org/W2794103424","https://openalex.org/W1996530509","https://openalex.org/W3028317537","https://openalex.org/W2389515972","https://openalex.org/W4245435724","https://openalex.org/W2055301889","https://openalex.org/W4400979532","https://openalex.org/W2376554934","https://openalex.org/W2077790809","https://openalex.org/W1505959757"],"abstract_inverted_index":{"Many":[0],"semi-conductor":[1],"manufacturing":[2],"companies":[3],"use":[4],"3D":[5,61],"interconnect":[6,62],"technology":[7],"to":[8,50,59],"flexibly":[9],"combine":[10],"smaller":[11],"heterogeneous":[12],"designs":[13],"in":[14],"a":[15,47,57,83],"system-on-package.":[16],"Internal":[17],"I/O":[18],"(IIO)":[19],"are":[20],"placed":[21],"at":[22],"two":[23],"ends":[24],"of":[25,31,43],"the":[26,39,67],"inter-die":[27,44],"interconnect.":[28],"Small":[29],"dimension":[30],"IIOs":[32],"prohibits":[33],"tester":[34],"probing.":[35],"This,":[36],"along":[37],"with":[38],"very":[40],"large":[41],"number":[42],"interconnects":[45],"poses":[46],"serious":[48],"challenge":[49],"robustly":[51],"test":[52],"these":[53],"interconnects.":[54],"This":[55,64],"is":[56,90],"hindrance":[58],"adopting":[60,87],"technologies.":[63],"paper":[65],"discusses":[66],"difference":[68],"between":[69],"IIO":[70,78],"testing":[71],"and":[72],"GPIO,":[73],"HSIO":[74],"testing.":[75],"A":[76],"novel":[77],"BIST":[79],"solution,":[80],"which":[81],"removes":[82],"major":[84],"obstacle":[85],"for":[86],"3D-interconnect":[88],"technology,":[89],"presented.":[91]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
