{"id":"https://openalex.org/W2958559473","doi":"https://doi.org/10.1109/vts.2019.8758655","title":"Innovative Practices on DFT for AI Chips","display_name":"Innovative Practices on DFT for AI Chips","publication_year":2019,"publication_date":"2019-04-01","ids":{"openalex":"https://openalex.org/W2958559473","doi":"https://doi.org/10.1109/vts.2019.8758655","mag":"2958559473"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2019.8758655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2019.8758655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 37th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103089326","display_name":"Iris Ma","orcid":"https://orcid.org/0009-0003-3699-7981"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Iris Ma","raw_affiliation_strings":["Enflame Technology, P. R. China"],"affiliations":[{"raw_affiliation_string":"Enflame Technology, P. R. China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108264709","display_name":"Hui King Lau","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139321","display_name":"Graphcore (United Kingdom)","ror":"https://ror.org/03b3h3q73","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210139321"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Hui King Lau","raw_affiliation_strings":["Graphcore, U.K"],"affiliations":[{"raw_affiliation_string":"Graphcore, U.K","institution_ids":["https://openalex.org/I4210139321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022166482","display_name":"Joseph Reynick","orcid":"https://orcid.org/0000-0002-3215-1212"},"institutions":[{"id":"https://openalex.org/I4210100005","display_name":"Silicon Technologies (United States)","ror":"https://ror.org/013qwzt07","country_code":"US","type":"company","lineage":["https://openalex.org/I4210100005"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joseph Reynick","raw_affiliation_strings":["eSilicon, USA"],"affiliations":[{"raw_affiliation_string":"eSilicon, USA","institution_ids":["https://openalex.org/I4210100005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101775144","display_name":"Yu Huang","orcid":"https://orcid.org/0000-0003-2619-4686"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Huang","raw_affiliation_strings":["Mentor, A Siemens Business, USA (Organizer)"],"affiliations":[{"raw_affiliation_string":"Mentor, A Siemens Business, USA (Organizer)","institution_ids":["https://openalex.org/I4210137693"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103089326"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.47847639,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6544173359870911},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.6085333824157715},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5715571045875549},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.5525993704795837},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.4704393744468689},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36466729640960693},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34063318371772766},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.32072824239730835},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1955111026763916},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13487955927848816},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.12122061848640442}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6544173359870911},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.6085333824157715},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5715571045875549},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.5525993704795837},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.4704393744468689},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36466729640960693},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34063318371772766},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.32072824239730835},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1955111026763916},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13487955927848816},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.12122061848640442},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2019.8758655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2019.8758655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 37th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4230197055","https://openalex.org/W4296749040","https://openalex.org/W621808327","https://openalex.org/W644007644","https://openalex.org/W2497198634","https://openalex.org/W3012257603","https://openalex.org/W1586784764","https://openalex.org/W1987342913","https://openalex.org/W2725956529","https://openalex.org/W2117241246"],"abstract_inverted_index":{"Hardware":[0],"acceleration":[1],"for":[2,24,80],"Artificial":[3],"Intelligence":[4],"(AI)":[5],"is":[6,20,77],"now":[7],"a":[8,16,21,67,70],"very":[9,49,71,78],"competitive":[10],"and":[11,31,41,54],"rapidly":[12],"evolving":[13],"market.":[14],"As":[15],"result,":[17],"fast":[18],"time-to-market":[19,30],"leading":[22],"concern":[23],"this":[25,96],"segment.":[26],"To":[27],"speed":[28],"up":[29],"ensure":[32],"quality,":[33],"new":[34,38,85],"design-for-test":[35],"(DFT)":[36],"architectures,":[37],"DFT":[39,93,103,115],"methodologies":[40],"technologies":[42],"are":[43,47],"emerging.":[44],"AI":[45,107,117],"chips":[46],"typically":[48],"big":[50],"with":[51],"many":[52],"identical":[53,56],"non-":[55],"cores,":[57],"distributed":[58],"memories,":[59],"high-speed":[60],"IOs,":[61],"which":[62],"makes":[63],"testing":[64],"of":[65,90,92,114],"such":[66],"gigantic":[68],"SoC":[69],"challenging":[72],"task.":[73],"We":[74],"found":[75],"it":[76],"important":[79],"us":[81],"to":[82,110],"understand":[83],"these":[84],"challenges":[86],"from":[87,105],"the":[88],"point":[89],"views":[91],"engineers.":[94],"In":[95],"innovative":[97],"practice":[98],"session,":[99],"we":[100],"invited":[101],"three":[102,106],"experts":[104],"chip":[108],"companies":[109],"share":[111],"their":[112],"experiences":[113],"on":[116],"chips.":[118]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}