{"id":"https://openalex.org/W2806223883","doi":"https://doi.org/10.1109/vts.2018.8368637","title":"Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits","display_name":"Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits","publication_year":2018,"publication_date":"2018-04-01","ids":{"openalex":"https://openalex.org/W2806223883","doi":"https://doi.org/10.1109/vts.2018.8368637","mag":"2806223883"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2018.8368637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2018.8368637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 36th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025777269","display_name":"Omar Al-Terkawi Hasib","orcid":"https://orcid.org/0000-0001-9842-8299"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Omar Al-Terkawi Hasib","raw_affiliation_strings":["\u00c9cole Polytechnique of Montr\u00e9al, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique of Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030885771","display_name":"Daniel Crepeau","orcid":null},"institutions":[{"id":"https://openalex.org/I4210166269","display_name":"Octane (Canada)","ror":"https://ror.org/05xt51492","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210166269"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Daniel Crepeau","raw_affiliation_strings":["Octasic, Canada"],"affiliations":[{"raw_affiliation_string":"Octasic, Canada","institution_ids":["https://openalex.org/I4210166269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065861313","display_name":"Thomas Awad","orcid":null},"institutions":[{"id":"https://openalex.org/I4210166269","display_name":"Octane (Canada)","ror":"https://ror.org/05xt51492","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210166269"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Thomas Awad","raw_affiliation_strings":["Octasic, Canada"],"affiliations":[{"raw_affiliation_string":"Octasic, Canada","institution_ids":["https://openalex.org/I4210166269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006847558","display_name":"Andrei Dulipovici","orcid":null},"institutions":[{"id":"https://openalex.org/I9736820","display_name":"\u00c9cole de Technologie Sup\u00e9rieure","ror":"https://ror.org/0020snb74","country_code":"CA","type":"education","lineage":["https://openalex.org/I49663120","https://openalex.org/I9736820"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andrei Dulipovici","raw_affiliation_strings":["\u00c9cole de Technologie Sup\u00e9rieure, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole de Technologie Sup\u00e9rieure, Canada","institution_ids":["https://openalex.org/I9736820"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["\u00c9cole Polytechnique of Montr\u00e9al, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique of Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065451135","display_name":"Claude Thibeault","orcid":"https://orcid.org/0000-0003-1765-9170"},"institutions":[{"id":"https://openalex.org/I9736820","display_name":"\u00c9cole de Technologie Sup\u00e9rieure","ror":"https://ror.org/0020snb74","country_code":"CA","type":"education","lineage":["https://openalex.org/I49663120","https://openalex.org/I9736820"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Claude Thibeault","raw_affiliation_strings":["\u00c9cole de Technologie Sup\u00e9rieure, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole de Technologie Sup\u00e9rieure, Canada","institution_ids":["https://openalex.org/I9736820"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5025777269"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.7881,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.69617915,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6764581203460693},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6075515151023865},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46838217973709106},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28527823090553284},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2507190704345703}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6764581203460693},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6075515151023865},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46838217973709106},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28527823090553284},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2507190704345703}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/vts.2018.8368637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2018.8368637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 36th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},{"id":"pmh:oai:espace2.etsmtl.ca:17152","is_oa":false,"landing_page_url":"http://espace2.etsmtl.ca/id/eprint/17152/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402392","display_name":"Espace \u00c9TS (ETS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1341030882","host_organization_name":"Educational Testing Service","host_organization_lineage":["https://openalex.org/I1341030882"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Compte rendu de conf\u00e9rence"},{"id":"pmh:oai:publications.polymtl.ca:40397","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/40397/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5199999809265137}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310638","display_name":"McGill University","ror":"https://ror.org/01pxwe438"},{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1542879788","https://openalex.org/W1569705806","https://openalex.org/W1980985044","https://openalex.org/W1982904663","https://openalex.org/W2059016802","https://openalex.org/W2078037485","https://openalex.org/W2096146619","https://openalex.org/W2110259743","https://openalex.org/W2120511589","https://openalex.org/W2152321821","https://openalex.org/W2404733959","https://openalex.org/W4244741468","https://openalex.org/W4248814671"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2478288626","https://openalex.org/W4391913857","https://openalex.org/W2350741829","https://openalex.org/W4241196849"],"abstract_inverted_index":{"The":[0,34,91,111],"application":[1,60],"of":[2,37,44,54,61,72,87],"scan-based":[3,74,97],"at-speed":[4,38,62,75],"delay":[5,89],"testing":[6,63,76,98],"on":[7,64,77,116,145],"asynchronous":[8,65,82],"circuits":[9,83,117],"is":[10,114,130],"not":[11],"trivial.":[12],"Their":[13],"unorthodox":[14],"design":[15,23],"leaves":[16],"them":[17],"generally":[18],"incompatible":[19],"with":[20,99,141],"traditional":[21],"synchronous":[22],"and":[24,41,102,137],"test":[25,32,39,47,93,105,113,135,143],"tools,":[26],"as":[27,29],"well":[28],"standard":[30],"automatic":[31,46],"equipment.":[33],"correct":[35],"generation":[36,49],"clocks":[40],"the":[42,55,59,104,133],"use":[43],"conventional":[45,108],"patterns":[48,106],"(ATPG)":[50],"tools":[51],"are":[52],"some":[53],"problems":[56],"that":[57],"face":[58],"circuits.":[66],"This":[67,128],"paper":[68],"presents":[69],"a":[70,119,146],"method":[71,94,129],"applying":[73],"single-rail":[78],"bundleddata":[79],"handshake-free":[80],"(self-timed)":[81],"by":[84,132],"taking":[85],"advantage":[86],"built-in":[88],"lines.":[90],"proposed":[92,112],"uses":[95],"launch-on-capture":[96],"endpoint":[100],"masking":[101],"generates":[103],"using":[107],"ATPG":[109],"tools.":[110],"applied":[115],"in":[118,123],"self-timed":[120],"microprocessor":[121],"fabricated":[122],"28nm":[124],"FD-SOI":[125],"CMOS":[126],"technology.":[127],"validated":[131],"reported":[134],"coverage":[136],"simulation":[138],"results,":[139],"along":[140],"post-silicon":[142],"results":[144],"Teradyne":[147],"FLEX":[148],"tester.":[149]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}