{"id":"https://openalex.org/W2397017703","doi":"https://doi.org/10.1109/vts.2016.7477308","title":"Flexible scan interface architecture for complex SoCs","display_name":"Flexible scan interface architecture for complex SoCs","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2397017703","doi":"https://doi.org/10.1109/vts.2016.7477308","mag":"2397017703"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2016.7477308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2016.7477308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113516558","display_name":"Milind Sonawane","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Milind Sonawane","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065631513","display_name":"Sailendra Chadalavada","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sailendra Chadalavada","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009749203","display_name":"Shantanu Sarangi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shantanu Sarangi","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060188846","display_name":"Amit Sanghani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Sanghani","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043179142","display_name":"Mahmut Yilmaz","orcid":"https://orcid.org/0000-0002-4522-7028"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mahmut Yilmaz","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041362633","display_name":"Pavan Kumar Datla Jagannadha","orcid":"https://orcid.org/0009-0007-7962-3727"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pavan Kumar Datla Jagannadha","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070673314","display_name":"J.E. Colburn","orcid":"https://orcid.org/0009-0007-2166-6281"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathon E. Colburn","raw_affiliation_strings":["DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"DFT Engineering, NVIDIA Corp, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5113516558"],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":1.2613,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77731804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.739962100982666},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.7041728496551514},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6225366592407227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5880364179611206},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5678034424781799},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5025143623352051},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.4180656969547272},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39527207612991333},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3683246970176697},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2670876979827881},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.15237706899642944},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.14076128602027893},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07873550057411194}],"concepts":[{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.739962100982666},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.7041728496551514},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6225366592407227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5880364179611206},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5678034424781799},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5025143623352051},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.4180656969547272},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39527207612991333},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3683246970176697},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2670876979827881},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.15237706899642944},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.14076128602027893},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07873550057411194},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2016.7477308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2016.7477308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1487165447","https://openalex.org/W1574592983","https://openalex.org/W1917503894","https://openalex.org/W1928666065","https://openalex.org/W2015184298","https://openalex.org/W2039336669","https://openalex.org/W2095894154","https://openalex.org/W2096979377","https://openalex.org/W2101900253","https://openalex.org/W2112041422","https://openalex.org/W2137590729","https://openalex.org/W2138784704","https://openalex.org/W2140035276","https://openalex.org/W2150516314","https://openalex.org/W2156412034","https://openalex.org/W2159594558","https://openalex.org/W2163417450","https://openalex.org/W4233842484","https://openalex.org/W6683904505"],"related_works":["https://openalex.org/W79379040","https://openalex.org/W2046542368","https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049","https://openalex.org/W2136848245","https://openalex.org/W4213404769"],"abstract_inverted_index":{"Non-standardized":[0],"scan":[1,25,41,66,80],"interface":[2,26],"within":[3],"and":[4,23],"across":[5,37,55],"system-on-chips":[6],"(SoCs)":[7],"limits":[8],"test-data":[9,32],"reuse":[10,30],"for":[11,33],"intellectual":[12],"properties":[13],"(IPs).":[14],"To":[15],"overcome":[16],"this":[17,48],"limitation,":[18],"we":[19],"present":[20],"a":[21,34,59],"flexible":[22],"dynamic":[24,45],"architecture":[27,49,63],"that":[28],"enables":[29,51],"of":[31,47,73],"given":[35,60],"IP":[36],"SoCs":[38],"with":[39],"different":[40,56],"pin":[42,67],"configurations.":[43],"The":[44,62],"nature":[46],"also":[50,77],"variable":[52],"shift":[53],"frequencies":[54],"IPs":[57],"in":[58],"SoC.":[61],"decouples":[64],"the":[65,70,74],"requirements":[68],"from":[69],"design":[71],"cycle":[72],"IPs.":[75],"It":[76],"uses":[78],"bidirectional":[79],"pins":[81],"to":[82],"further":[83],"reduce":[84],"test":[85],"cost":[86],"by":[87],"using":[88],"as":[89,91],"few":[90],"two":[92],"pins.":[93]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}