{"id":"https://openalex.org/W2402682918","doi":"https://doi.org/10.1109/vts.2016.7477261","title":"A novel technique for interdependent trim code optimization","display_name":"A novel technique for interdependent trim code optimization","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2402682918","doi":"https://doi.org/10.1109/vts.2016.7477261","mag":"2402682918"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2016.7477261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2016.7477261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087135213","display_name":"Pankaj Bongale","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pankaj Bongale","raw_affiliation_strings":["Texas Instruments (India) Pvt. Ltd., Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049247165","display_name":"Vinothkumar Sundaresan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vinothkumar Sundaresan","raw_affiliation_strings":["Tessolve Services Pvt. Ltd., Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tessolve Services Pvt. Ltd., Bengaluru, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001735719","display_name":"Partha Ghosh","orcid":"https://orcid.org/0000-0003-4808-3370"},"institutions":[{"id":"https://openalex.org/I2799323385","display_name":"Board of the Swiss Federal Institutes of Technology","ror":"https://ror.org/01rvn4p91","country_code":"CH","type":"government","lineage":["https://openalex.org/I2799323385"]},{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Partha Ghosh","raw_affiliation_strings":["Eidgenssische Technische Hochschule (ETH), Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eidgenssische Technische Hochschule (ETH), Zurich, Switzerland","institution_ids":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028519358","display_name":"Rubin Parekhji","orcid":"https://orcid.org/0009-0000-6625-2786"},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rubin Parekhji","raw_affiliation_strings":["Texas Instruments (India) Pvt. Ltd., Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/trim","display_name":"Trim","score":0.8267097473144531},{"id":"https://openalex.org/keywords/trimming","display_name":"Trimming","score":0.7834028005599976},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6805962920188904},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5543161630630493},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5307697653770447},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5178385376930237},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4972567856311798},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48721426725387573},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4823403060436249},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47809359431266785},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4155694842338562},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4153633415699005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4045405387878418},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3299141526222229},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20736342668533325},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09638753533363342},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09286180138587952}],"concepts":[{"id":"https://openalex.org/C88611116","wikidata":"https://www.wikidata.org/wiki/Q957004","display_name":"Trim","level":2,"score":0.8267097473144531},{"id":"https://openalex.org/C56951928","wikidata":"https://www.wikidata.org/wiki/Q3539213","display_name":"Trimming","level":2,"score":0.7834028005599976},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6805962920188904},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5543161630630493},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5307697653770447},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5178385376930237},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4972567856311798},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48721426725387573},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4823403060436249},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47809359431266785},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4155694842338562},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4153633415699005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4045405387878418},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3299141526222229},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20736342668533325},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09638753533363342},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09286180138587952},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2016.7477261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2016.7477261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1575223513","https://openalex.org/W1596965972","https://openalex.org/W1967985516","https://openalex.org/W2015680436","https://openalex.org/W2053130521","https://openalex.org/W2056358418","https://openalex.org/W2167973072","https://openalex.org/W2171074980","https://openalex.org/W2432517183","https://openalex.org/W2612977707","https://openalex.org/W2981264952","https://openalex.org/W4205302594","https://openalex.org/W4205920538"],"related_works":["https://openalex.org/W2483447122","https://openalex.org/W4205838487","https://openalex.org/W2467235537","https://openalex.org/W4243755427","https://openalex.org/W4320062971","https://openalex.org/W4206542901","https://openalex.org/W2048650805","https://openalex.org/W2052775810","https://openalex.org/W644125712","https://openalex.org/W571254925"],"abstract_inverted_index":{"As":[0],"integrated":[1],"circuits":[2,18],"become":[3],"increasingly":[4],"complex,":[5],"the":[6,51,71,78,103,107,115,142],"fabrication":[7,24],"process":[8,28,42],"renders":[9],"them":[10],"more":[11,88],"marginal":[12],"to":[13,20,25,38,101],"specification":[14],"parameters.":[15],"Consequently,":[16],"these":[17,68],"have":[19],"be":[21,94,136],"tuned":[22],"post":[23],"compensate":[26],"for":[27,91,128],"marginality":[29],"and":[30,60,97,133,164],"thereby":[31],"optimize":[32],"their":[33],"performance":[34,105,167],"as":[35,37,48,62,139],"well":[36],"improve":[39],"yields.":[40],"This":[41,75,124],"of":[43,54,80,106,114,141,159],"tuning":[44],"is":[45,58,122,126],"commonly":[46],"termed":[47],"trimming,":[49],"wherein":[50],"right":[52],"set":[53],"digital":[55],"trim":[56,160],"codes":[57,69,90],"identified":[59],"used":[61],"a":[63],"calibration":[64],"setting":[65],"by":[66],"writing":[67],"into":[70],"hardware":[72,112],"configuration":[73],"registers.":[74],"paper":[76],"addresses":[77],"problem":[79],"carrying":[81],"out":[82],"multi-variable":[83],"trims":[84],"involving":[85],"two":[86,153],"or":[87],"parameters,":[89],"which":[92],"must":[93],"simultaneously":[95],"searched":[96],"set,":[98],"in":[99,157],"order":[100],"attain":[102],"desired":[104],"circuit.":[108],"A":[109],"novel":[110],"low-cost":[111],"implementation":[113,125],"Simplex":[116],"minimization":[117],"algorithm":[118],"with":[119],"speed-up":[120],"improvements":[121],"described.":[123],"amenable":[127],"on-chip":[129],"BIST":[130],"(built-in":[131],"self-test)":[132],"can":[134],"also":[135],"directly":[137],"implemented":[138],"part":[140],"ATE":[143],"(automatic":[144],"test":[145],"equipment)":[146],"program.":[147],"Experimental":[148],"results":[149],"are":[150,168],"presented":[151],"on":[152],"industrial":[154],"circuits.":[155],"Improvements":[156],"terms":[158],"code":[161],"search":[162],"time":[163],"attaining":[165],"better":[166],"shown.":[169]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
