{"id":"https://openalex.org/W1490997466","doi":"https://doi.org/10.1109/vts.2015.7116287","title":"Random pattern generation for post-silicon validation of DDR3 SDRAM","display_name":"Random pattern generation for post-silicon validation of DDR3 SDRAM","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1490997466","doi":"https://doi.org/10.1109/vts.2015.7116287","mag":"1490997466"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2015.7116287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2015.7116287","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100642435","display_name":"Haoyu Yang","orcid":"https://orcid.org/0000-0002-4709-0061"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hao-Yu Yang","raw_affiliation_strings":["Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056318989","display_name":"Shih-Hua Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Hua Kuo","raw_affiliation_strings":["Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040415114","display_name":"Tzu\u2010Hsuan Huang","orcid":"https://orcid.org/0000-0002-9483-8263"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tzu-Hsuan Huang","raw_affiliation_strings":["Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100804064","display_name":"Chi-Hung Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]},{"id":"https://openalex.org/I2803006356","display_name":"Winbond (Taiwan)","ror":"https://ror.org/045100v05","country_code":"TW","type":"company","lineage":["https://openalex.org/I2803006356"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Hung Chen","raw_affiliation_strings":["Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Winbond Electronics Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Winbond Electronics Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I2803006356"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112471099","display_name":"Chris Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I2803006356","display_name":"Winbond (Taiwan)","ror":"https://ror.org/045100v05","country_code":"TW","type":"company","lineage":["https://openalex.org/I2803006356"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chris Lin","raw_affiliation_strings":["Winbond Electronics Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Winbond Electronics Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I2803006356"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045156360","display_name":"Mango C.-T. Chao","orcid":"https://orcid.org/0000-0002-7299-9015"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]},{"id":"https://openalex.org/I2803006356","display_name":"Winbond (Taiwan)","ror":"https://ror.org/045100v05","country_code":"TW","type":"company","lineage":["https://openalex.org/I2803006356"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mango C.-T. Chao","raw_affiliation_strings":["Winbond Electronics Corporation, Hsinchu, Taiwan","Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Winbond Electronics Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I2803006356"]},{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3294,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5693437,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8672951459884644},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.7254757881164551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7184036374092102},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7046337127685547},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.6235656142234802},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5144076943397522},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49683669209480286},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3754673898220062},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.37295472621917725},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.26791292428970337},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.253821462392807},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14832213521003723},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.07662451267242432}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8672951459884644},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.7254757881164551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7184036374092102},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7046337127685547},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.6235656142234802},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5144076943397522},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49683669209480286},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3754673898220062},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.37295472621917725},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.26791292428970337},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.253821462392807},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14832213521003723},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.07662451267242432}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2015.7116287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2015.7116287","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1042992399","https://openalex.org/W1545427568","https://openalex.org/W2012432133","https://openalex.org/W2156560775","https://openalex.org/W2535248847"],"related_works":["https://openalex.org/W1976244802","https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W2547220881","https://openalex.org/W3140615508","https://openalex.org/W2532617734","https://openalex.org/W1603816627"],"abstract_inverted_index":{"Due":[0],"to":[1,48,74,96,107,146],"the":[2,19,28,52,100,103,108,116,121,129,143,148],"demand":[3],"of":[4,21,54,102,123,141],"pursuing":[5],"a":[6,72,81],"main":[7],"memory":[8],"with":[9,39,62],"larger":[10],"data":[11,14],"bandwidth,":[12],"higher":[13],"density,":[15],"and":[16,60,111],"lower":[17],"power,":[18],"specification":[20,117],"DRAM":[22,33],"has":[23],"been":[24],"constantly":[25],"evolved":[26],"in":[27,115],"past":[29],"decade.":[30],"The":[31,92],"new":[32],"specifications":[34],"support":[35],"multiple":[36,40],"operating":[37,56],"modes":[38],"timing":[41,58,112],"settings.":[42],"It":[43],"then":[44],"becomes":[45],"computationally":[46],"infeasible":[47],"exhaustively":[49],"validate":[50],"all":[51],"combinations":[53],"different":[55],"modes,":[57],"settings":[59],"address/data":[61],"pure":[63],"simulation":[64],"before":[65],"silicon.":[66],"In":[67],"this":[68],"paper,":[69],"we":[70],"propose":[71],"framework":[73,94,145],"generate":[75],"proper":[76],"random":[77],"patterns":[78,105],"for":[79,128],"validating":[80],"newly":[82],"designed":[83],"DDR3":[84,131,154],"SDRAM":[85,155],"based":[86,151],"on":[87,152],"its":[88],"first":[89],"silicon":[90],"chips.":[91],"proposed":[93,144],"needs":[95],"not":[97],"only":[98],"guarantee":[99],"correctness":[101],"generated":[104],"according":[106],"state":[109],"diagram":[110],"constraints":[113],"defined":[114],"but":[118],"also":[119,135],"provide":[120],"flexibility":[122],"exploring":[124],"various":[125],"design":[126,149],"corners":[127],"targeted":[130],"SDRAM.":[132],"We":[133],"will":[134],"show":[136],"some":[137],"successful":[138],"silicon-validation":[139],"cases":[140],"applying":[142],"identify":[147],"errors":[150],"real":[153],"products.":[156]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
