{"id":"https://openalex.org/W1499133832","doi":"https://doi.org/10.1109/vts.2015.7116282","title":"Innovative practices session 7C: Mixed signal test and debug","display_name":"Innovative practices session 7C: Mixed signal test and debug","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1499133832","doi":"https://doi.org/10.1109/vts.2015.7116282","mag":"1499133832"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2015.7116282","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2015.7116282","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113896083","display_name":"S. Natarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I139759216","display_name":"Beijing University of Posts and Telecommunications","ror":"https://ror.org/04w9fbh59","country_code":"CN","type":"education","lineage":["https://openalex.org/I139759216"]}],"countries":["CN","US"],"is_corresponding":true,"raw_author_name":"Suriya Natarajan","raw_affiliation_strings":["Beijing Key Laboratory of Network System Architecture and Convergence, Beijing University of Posts and Telecommunications, Beijing, China","Intel USA"],"affiliations":[{"raw_affiliation_string":"Beijing Key Laboratory of Network System Architecture and Convergence, Beijing University of Posts and Telecommunications, Beijing, China","institution_ids":["https://openalex.org/I139759216"]},{"raw_affiliation_string":"Intel USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113896083"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I139759216"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01946472,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9850999712944031,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9850999712944031,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9825000166893005,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12111","display_name":"Industrial Vision Systems and Defect Detection","score":0.9722999930381775,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.743234395980835},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6084840893745422},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.6034654378890991},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6030139923095703},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5183618664741516},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5131519436836243},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5047026872634888},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43489718437194824},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39582914113998413},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.37475988268852234},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2828105390071869},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.25761914253234863},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15556254982948303}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.743234395980835},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6084840893745422},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.6034654378890991},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6030139923095703},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5183618664741516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5131519436836243},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5047026872634888},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43489718437194824},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39582914113998413},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.37475988268852234},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2828105390071869},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.25761914253234863},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15556254982948303},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2015.7116282","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2015.7116282","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W2611067230","https://openalex.org/W2480201319","https://openalex.org/W2387706296","https://openalex.org/W2155788121","https://openalex.org/W4235469518","https://openalex.org/W362492756","https://openalex.org/W2294325978"],"abstract_inverted_index":{"The":[0,70],"traditional":[1],"focus":[2],"of":[3,23,53,94],"work":[4],"in":[5,18,65,77,79],"test":[6,41,111],"has":[7,86],"been":[8],"innovation":[9],"and":[10,30,36,63,109,113,121],"efficiency":[11],"for":[12,102,119],"high":[13,37],"volume":[14],"manufacturing":[15,68,110],"test.":[16,69],"However,":[17],"reality,":[19],"a":[20,91,127],"significant":[21],"amount":[22],"effort":[24],"is":[25,75],"expended":[26],"on":[27,72,126],"design":[28,61,107],"validation":[29,62,108],"debug":[31,64],"prior":[32],"to":[33,58,67,81,87],"deeming":[34],"analog":[35,120],"speed":[38],"serial":[39],"IO":[40,122],"stimuli":[42],"content":[43,123],"production":[44],"worthy.":[45],"In":[46],"this":[47],"presentation":[48],"we":[49],"emphasize":[50],"the":[51,55,84,100,114],"importance":[52],"widening":[54],"post-silicon":[56,95],"envelope":[57],"include":[59],"early":[60],"addition":[66],"impact":[71],"DFX":[73],"architecture":[74,85],"considered":[76],"which":[78],"order":[80],"be":[82,88],"efficient":[83],"scalable":[89],"across":[90],"wider":[92],"set":[93],"stages.":[96],"We":[97],"also":[98],"discuss":[99],"need":[101],"establishing":[103],"quick":[104],"correlation":[105],"between":[106],"measurements":[112],"time-to-market":[115],"savings":[116],"it":[117],"brings":[118],"designed":[124],"essentially":[125],"digital":[128],"process":[129],"technology.":[130]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}