{"id":"https://openalex.org/W2004094856","doi":"https://doi.org/10.1109/vts.2014.6818781","title":"Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test","display_name":"Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test","publication_year":2014,"publication_date":"2014-04-01","ids":{"openalex":"https://openalex.org/W2004094856","doi":"https://doi.org/10.1109/vts.2014.6818781","mag":"2004094856"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2014.6818781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2014.6818781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110125765","display_name":"Masahiro Ishida","orcid":"https://orcid.org/0009-0003-7497-1053"},"institutions":[{"id":"https://openalex.org/I177844149","display_name":"Advantest (Singapore)","ror":"https://ror.org/04dyk5z88","country_code":"SG","type":"company","lineage":["https://openalex.org/I177844149","https://openalex.org/I4210103901"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Masahiro Ishida","raw_affiliation_strings":["ADVANTEST Corporation","ADVANTEST Corporation,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ADVANTEST Corporation","institution_ids":["https://openalex.org/I177844149"]},{"raw_affiliation_string":"ADVANTEST Corporation,","institution_ids":["https://openalex.org/I177844149"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010763159","display_name":"Takahiro Yamaguchi","orcid":"https://orcid.org/0000-0003-0325-8878"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Takahiro J. Yamaguchi","raw_affiliation_strings":["ADVANTEST Laboratories, Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ADVANTEST Laboratories, Ltd","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112265787","display_name":"M. Soma","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mani Soma","raw_affiliation_strings":["Washington University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015514585","display_name":"T.S. Fiez","orcid":"https://orcid.org/0000-0003-3596-2472"},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Terri Fiez","raw_affiliation_strings":["Oregon State University","Oregon State University>"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Oregon State University","institution_ids":["https://openalex.org/I131249849"]},{"raw_affiliation_string":"Oregon State University>","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002311924","display_name":"Mike Peng Li","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike Peng Li","raw_affiliation_strings":["Altera Corporation","Altera Corporation#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Altera Corporation","institution_ids":["https://openalex.org/I22433950"]},{"raw_affiliation_string":"Altera Corporation#TAB#","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9860000014305115,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.829830527305603},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.7505968809127808},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5912893414497375},{"id":"https://openalex.org/keywords/test-design","display_name":"Test design","score":0.5716309547424316},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5484203100204468},{"id":"https://openalex.org/keywords/pace","display_name":"Pace","score":0.49043866991996765},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.47155189514160156},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.44630593061447144},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29834502935409546},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.2635412812232971},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.18900352716445923},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.16966676712036133},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12089195847511292}],"concepts":[{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.829830527305603},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.7505968809127808},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5912893414497375},{"id":"https://openalex.org/C11017329","wikidata":"https://www.wikidata.org/wiki/Q7705763","display_name":"Test design","level":3,"score":0.5716309547424316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5484203100204468},{"id":"https://openalex.org/C2777526511","wikidata":"https://www.wikidata.org/wiki/Q691543","display_name":"Pace","level":2,"score":0.49043866991996765},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.47155189514160156},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.44630593061447144},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29834502935409546},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.2635412812232971},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.18900352716445923},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.16966676712036133},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12089195847511292},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2014.6818781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2014.6818781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2002228152","https://openalex.org/W615030097","https://openalex.org/W2099425240","https://openalex.org/W2273696519","https://openalex.org/W1533203477","https://openalex.org/W4231573368","https://openalex.org/W2101175460","https://openalex.org/W2149715677","https://openalex.org/W2031405636","https://openalex.org/W1917826435"],"abstract_inverted_index":{"Recent":[0],"analog":[1,53,89],"designers":[2,54,99],"do":[3],"think":[4],"about":[5],"measurement":[6],"at":[7],"design":[8,49,74],"time.":[9],"Analog":[10],"design-for-measurement":[11],"is":[12],"a":[13,82],"real":[14],"success,":[15],"not":[16,44],"based":[17,22],"on":[18,23,88,97],"test":[19,41,85,101],"research":[20,42],"but":[21],"designers'":[24,83],"incorporation":[25],"of":[26],"calibration":[27],"methods":[28],"to":[29],"ensure":[30],"that":[31],"their":[32],"circuits":[33],"work":[34],"within":[35],"specifications.":[36],"In":[37],"the":[38,64,71,78],"meantime,":[39],"mixed-signal":[40,57],"has":[43],"kept":[45],"pace":[46],"with":[47],"new":[48],"architectures,":[50],"and":[51,70,75,84,94,100],"some":[52,95],"have":[55],"outpaced":[56],"test/design-for-test":[58],"researchers.":[59,102],"This":[60],"session":[61,79],"will":[62,80],"elucidate":[63],"key":[65],"factors":[66],"for":[67],"this":[68],"success":[69],"differences":[72],"between":[73],"test.":[76],"And":[77],"discusses":[81],"researchers'":[86],"roles":[87],"design-for-test":[90],"from":[91],"each":[92],"viewpoint,":[93],"challenges":[96],"collaborating":[98]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}