{"id":"https://openalex.org/W2087377347","doi":"https://doi.org/10.1109/vts.2013.6548940","title":"Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs","display_name":"Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2087377347","doi":"https://doi.org/10.1109/vts.2013.6548940","mag":"2087377347"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2013.6548940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2013.6548940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081576356","display_name":"Chih-Sheng Hou","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chih-Sheng Hou","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jhong li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhong li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100741015","display_name":"Jingfu Li","orcid":"https://orcid.org/0000-0002-0079-9129"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Fu Li","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jhong li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhong li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081576356"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":1.1822,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.81872992,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.6531627774238586},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5259178876876831},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4329472482204437},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4132322669029236},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3429490029811859},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2560439109802246}],"concepts":[{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.6531627774238586},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5259178876876831},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4329472482204437},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4132322669029236},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3429490029811859},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2560439109802246}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2013.6548940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2013.6548940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[{"id":"https://openalex.org/F4320324262","display_name":"Birla Institute of Scientific Research","ror":"https://ror.org/0203yhg37"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1563309336","https://openalex.org/W1792362277","https://openalex.org/W1922918362","https://openalex.org/W1971966678","https://openalex.org/W1973508428","https://openalex.org/W2005160252","https://openalex.org/W2026717319","https://openalex.org/W2060071452","https://openalex.org/W2079486027","https://openalex.org/W2094915857","https://openalex.org/W2102048395","https://openalex.org/W2102136494","https://openalex.org/W2114185924","https://openalex.org/W2114930002","https://openalex.org/W2115013189","https://openalex.org/W2116273964","https://openalex.org/W2118898957","https://openalex.org/W2119482888","https://openalex.org/W2121938580","https://openalex.org/W2124479423","https://openalex.org/W2132635813","https://openalex.org/W2134822007","https://openalex.org/W2137795611","https://openalex.org/W2138246797","https://openalex.org/W2141400030","https://openalex.org/W2149233130","https://openalex.org/W2157130998","https://openalex.org/W2171372273","https://openalex.org/W3142145731","https://openalex.org/W6675341223","https://openalex.org/W6677639902","https://openalex.org/W6677993950"],"related_works":["https://openalex.org/W2142462517","https://openalex.org/W1485942900","https://openalex.org/W1826635240","https://openalex.org/W2146606382","https://openalex.org/W2110446288","https://openalex.org/W3215142653","https://openalex.org/W2150113875","https://openalex.org/W1487051936","https://openalex.org/W2025912852","https://openalex.org/W194748710"],"abstract_inverted_index":{"A":[0],"modern":[1],"system-on-chip":[2],"(SOC)":[3],"may":[4],"become":[5],"one":[6],"of":[7,10,31,65,77,100,119,130],"the":[8,29,57,63,72,80,94,103,117,125,128,139,171,177],"dies":[9],"a":[11,34,39,52,86,109,152,160],"three-dimensional":[12],"(3D)":[13],"IC":[14],"using":[15],"through-silicon":[16],"via":[17],"(TSV).":[18],"Built-in":[19],"self-repair":[20],"(BISR)":[21],"techniques":[22],"have":[23],"been":[24],"widely":[25],"used":[26,91],"to":[27,44,92,115],"improve":[28],"yield":[30],"RAMs":[32,50,78,101,126],"in":[33,51,79,149],"SOC.":[35],"This":[36],"paper":[37],"proposes":[38],"memory":[40],"BISR":[41,47,66,122,140,154,162,173],"allocation":[42,179],"scheme":[43,155,174],"allocate":[45],"shared":[46,121,172],"circuits":[48,67,123],"for":[49,124],"SOC":[53],"die":[54],"such":[55],"that":[56,148],"test":[58,73,84,87,98,105,134,192],"and":[59,62,74,82,96,132,136,142,185,187,190],"repair":[60,75],"time":[61,76],"area":[64,165],"are":[68],"minimized.":[69],"To":[70],"minimize":[71],"pre-bond":[81,95,131,189],"post-bond":[83,97,133,191],"phases,":[85],"scheduling":[88],"engine":[89],"is":[90,113],"determine":[93],"sequences":[99,135],"under":[102,127,181],"corresponding":[104],"power":[106,193],"constraints.":[107],"Then,":[108],"BISR-circuit":[110],"minimization":[111],"algorithm":[112],"proposed":[114,178],"reduce":[116],"number":[118],"required":[120],"constraints":[129],"distance":[137,183],"between":[138],"circuit":[141],"served":[143],"RAMs.":[144],"Simulation":[145],"results":[146],"show":[147],"comparison":[150],"with":[151],"dedicated":[153],"(i.e.,":[156],"each":[157],"RAM":[158],"has":[159],"self-contained":[161],"circuit),":[163],"35%":[164],"reduction":[166],"can":[167],"be":[168],"achieved":[169],"by":[170,176],"planned":[175],"technique":[180],"lmm":[182],"constraint,":[184],"500mW":[186],"600mW":[188],"constraints,":[194],"respectively.":[195]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
