{"id":"https://openalex.org/W2016114271","doi":"https://doi.org/10.1109/vts.2012.6231105","title":"A SMT-based diagnostic test generation method for combinational circuits","display_name":"A SMT-based diagnostic test generation method for combinational circuits","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2016114271","doi":"https://doi.org/10.1109/vts.2012.6231105","mag":"2016114271"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2012.6231105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067318054","display_name":"Sarvesh Prabhu","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarvesh Prabhu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24060 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24060 USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael S. Hsiao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24060 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24060 USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090078841","display_name":"Loganathan Lingappan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Loganathan Lingappan","raw_affiliation_strings":["Intel Corporation, USA","Intel Corp., USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006680539","display_name":"Vijay Gangaram","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijay Gangaram","raw_affiliation_strings":["Intel Corporation, USA","Intel Corp., USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7047561407089233},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6806249022483826},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6399920582771301},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6275649666786194},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6090584993362427},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6075583696365356},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6041899919509888},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.592901885509491},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.567845344543457},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5586338639259338},{"id":"https://openalex.org/keywords/fault-simulator","display_name":"Fault Simulator","score":0.49072372913360596},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4772191643714905},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.47452273964881897},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.47063207626342773},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.47007399797439575},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4402664303779602},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.4284825921058655},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.4119386076927185},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3742952048778534},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.3119266927242279},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2746478319168091},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2696453332901001},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1485656499862671},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14409178495407104},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.0932483971118927}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7047561407089233},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6806249022483826},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6399920582771301},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6275649666786194},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6090584993362427},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6075583696365356},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6041899919509888},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.592901885509491},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.567845344543457},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5586338639259338},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.49072372913360596},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4772191643714905},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.47452273964881897},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.47063207626342773},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.47007399797439575},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4402664303779602},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.4284825921058655},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.4119386076927185},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3742952048778534},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.3119266927242279},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2746478319168091},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2696453332901001},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1485656499862671},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14409178495407104},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.0932483971118927},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2012.6231105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W92576581","https://openalex.org/W1507615093","https://openalex.org/W1819209966","https://openalex.org/W1843392114","https://openalex.org/W1987398152","https://openalex.org/W2011602485","https://openalex.org/W2079866295","https://openalex.org/W2106183788","https://openalex.org/W2142519941","https://openalex.org/W2146594632","https://openalex.org/W2150520488","https://openalex.org/W2167344937","https://openalex.org/W3205435241","https://openalex.org/W4231232119","https://openalex.org/W4246237793","https://openalex.org/W6802296934"],"related_works":["https://openalex.org/W4246671099","https://openalex.org/W2122643352","https://openalex.org/W2078848070","https://openalex.org/W2098411556","https://openalex.org/W2888456858","https://openalex.org/W2101853736","https://openalex.org/W2354343740","https://openalex.org/W2131499522","https://openalex.org/W2074302528","https://openalex.org/W2019719714"],"abstract_inverted_index":{"A":[0],"diagnostic":[1,79,86],"test":[2,87],"pattern":[3],"generator":[4],"using":[5],"a":[6,17,22,34],"Satisfiability":[7],"Modulo":[8],"Theory":[9],"(SMT)":[10],"solver":[11],"is":[12],"proposed.":[13],"Rather":[14],"than":[15],"targeting":[16],"single":[18,35],"fault":[19,31,53],"pair":[20],"at":[21],"time,":[23],"the":[24,43,49,67,95],"proposed":[25,40],"SMT":[26,44],"approach":[27],"can":[28,100],"distinguish":[29],"multiple":[30],"pairs":[32],"in":[33,94,103],"instance.":[36],"Several":[37],"heuristics":[38],"are":[39,81],"to":[41,46,91],"constrain":[42],"formula":[45],"further":[47],"reduce":[48],"search":[50],"space,":[51],"including":[52],"selection,":[54],"excitation":[55],"constraint,":[56],"reduced":[57],"primary":[58],"output":[59],"vector,":[60],"and":[61,69],"cone-of-influence":[62],"reduction.":[63],"Experimental":[64],"results":[65],"for":[66],"ISCAS85":[68],"full-scan":[70],"versions":[71],"of":[72,97],"ISCAS89":[73],"benchmark":[74],"circuits":[75],"show":[76],"that":[77],"fewer":[78],"vectors":[80,98],"generated":[82,99],"compared":[83],"with":[84],"conventional":[85],"generation":[88],"methods.":[89],"Up":[90],"73%":[92],"reduction":[93],"number":[96],"be":[101],"achieved":[102],"large":[104],"circuits.":[105]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}