{"id":"https://openalex.org/W2080818541","doi":"https://doi.org/10.1109/vts.2012.6231095","title":"Enhancing testability by structured partial scan","display_name":"Enhancing testability by structured partial scan","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2080818541","doi":"https://doi.org/10.1109/vts.2012.6231095","mag":"2080818541"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2012.6231095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065896534","display_name":"P. Wohl","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Wohl","raw_affiliation_strings":["Synopsys, Inc., USA","Synopsys Inc.USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys Inc.USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062016144","display_name":"J.A. Waicukauski","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Waicukauski","raw_affiliation_strings":["Synopsys, Inc., USA","Synopsys Inc.USA"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys Inc.USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070673314","display_name":"J.E. Colburn","orcid":"https://orcid.org/0009-0007-2166-6281"},"institutions":[{"id":"https://openalex.org/I1304085615","display_name":"Nvidia (United Kingdom)","ror":"https://ror.org/02kr42612","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]},{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"J.E. Colburn","raw_affiliation_strings":["NVIDIA Corporation, USA","[NVIDIA Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation, USA","institution_ids":["https://openalex.org/I4210127875"]},{"raw_affiliation_string":"[NVIDIA Corporation, USA]","institution_ids":["https://openalex.org/I1304085615"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065896534"],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.13996627,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"152","last_page":"157"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7492773532867432},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.712073802947998},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.6905181407928467},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6887998580932617},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6278999447822571},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6066609621047974},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6009876728057861},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5976424813270569},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.5938745141029358},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.5392493009567261},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.49615558981895447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19767320156097412},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.10812720656394958},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07689175009727478}],"concepts":[{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7492773532867432},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.712073802947998},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.6905181407928467},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6887998580932617},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6278999447822571},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6066609621047974},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6009876728057861},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5976424813270569},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.5938745141029358},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.5392493009567261},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.49615558981895447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19767320156097412},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.10812720656394958},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07689175009727478},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2012.6231095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W2073590490","https://openalex.org/W2074302528","https://openalex.org/W2097417935","https://openalex.org/W2117137640","https://openalex.org/W2124731399","https://openalex.org/W2131432014","https://openalex.org/W2134712318","https://openalex.org/W2136066342","https://openalex.org/W2142168082","https://openalex.org/W2156643581","https://openalex.org/W2160162958","https://openalex.org/W2164296477","https://openalex.org/W2165449398","https://openalex.org/W2166632412","https://openalex.org/W4247117539","https://openalex.org/W4247591377","https://openalex.org/W6668880913","https://openalex.org/W6680787594"],"related_works":["https://openalex.org/W2117171289","https://openalex.org/W1852363244","https://openalex.org/W1501621551","https://openalex.org/W2888456858","https://openalex.org/W2001654810","https://openalex.org/W2127184179","https://openalex.org/W2049913894","https://openalex.org/W2080818541","https://openalex.org/W2537616607","https://openalex.org/W1941705313"],"abstract_inverted_index":{"Full":[0],"scan":[1,25,36,42,53,90,104],"designs":[2,21,117],"are":[3],"widely":[4],"used":[5,38],"for":[6,19],"their":[7],"indisputable":[8],"benefits":[9],"of":[10,24,78],"predictably":[11],"high":[12],"test":[13,45,58,64,68,94],"coverage,":[14],"diagnosis":[15],"and":[16,28,34,56,66,70,110],"debug.":[17],"However,":[18],"high-performance":[20],"the":[22,87],"cost":[23],"-":[26,30],"area":[27],"delay":[29],"is":[31,37,96],"not":[32],"acceptable":[33],"partial":[35,41,52,103],"instead.":[39],"Unfortunately,":[40],"significantly":[43,62],"increases":[44],"generation":[46,59,95],"complexity.":[47],"We":[48],"define":[49],"a":[50,84],"structured":[51,102],"design":[54,73],"methodology":[55],"specific":[57],"enhancements,":[60],"which":[61,81],"enhance":[63],"coverage":[65,109],"reduce":[67],"data":[69],"cycles.":[71,92],"Selective":[72],"areas":[74],"use":[75],"special":[76],"types":[77],"nonscan":[79],"cells":[80],"can":[82],"capture":[83],"value":[85],"in":[86,107],"last":[88],"few":[89],"load":[91],"Combinational":[93],"extended":[97],"to":[98],"work":[99],"with":[100],"this":[101],"design,":[105],"resulting":[106],"higher":[108],"fewer":[111],"patterns.":[112],"Experimental":[113],"results":[114],"on":[115],"industrial":[116],"show":[118],"consistent":[119],"testability":[120],"benefits.":[121]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-01-13T01:12:25.745995","created_date":"2025-10-10T00:00:00"}
