{"id":"https://openalex.org/W2004458553","doi":"https://doi.org/10.1109/vts.2012.6231072","title":"A Built-In Self-Test scheme for DDR memory output timing test and measurement","display_name":"A Built-In Self-Test scheme for DDR memory output timing test and measurement","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2004458553","doi":"https://doi.org/10.1109/vts.2012.6231072","mag":"2004458553"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2012.6231072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100359545","display_name":"Hyunjin Kim","orcid":"https://orcid.org/0000-0001-6153-0521"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyunjin Kim","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, TX, USA","Computer Engineering Research Center, The University of Texas at Austin, University Station C8800, 78712, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Computer Engineering Research Center, The University of Texas at Austin, University Station C8800, 78712, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jacob A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, TX, USA","Computer Engineering Research Center, The University of Texas at Austin, University Station C8800, 78712, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Computer Engineering Research Center, The University of Texas at Austin, University Station C8800, 78712, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":null,"first_page":"7","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.675338625907898},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6141617298126221},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.543753981590271},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.4540362060070038},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45403194427490234},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4400281310081482},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.4176989197731018},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4170166552066803},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3790757656097412},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34200817346572876},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3379785418510437},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19069388508796692},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17757970094680786},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1442047357559204}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.675338625907898},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6141617298126221},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.543753981590271},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.4540362060070038},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45403194427490234},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4400281310081482},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.4176989197731018},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4170166552066803},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3790757656097412},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34200817346572876},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3379785418510437},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19069388508796692},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17757970094680786},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1442047357559204},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2012.6231072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2012.6231072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1544623790","https://openalex.org/W1563129028","https://openalex.org/W1604221342","https://openalex.org/W1916044672","https://openalex.org/W2013478191","https://openalex.org/W2015140511","https://openalex.org/W2063455737","https://openalex.org/W2101376128","https://openalex.org/W2104401999","https://openalex.org/W2114245605","https://openalex.org/W2129147891","https://openalex.org/W6633694044"],"related_works":["https://openalex.org/W2151858599","https://openalex.org/W2172451925","https://openalex.org/W2353619486","https://openalex.org/W2071924372","https://openalex.org/W4242565052","https://openalex.org/W2151732449","https://openalex.org/W1582186593","https://openalex.org/W1991670063","https://openalex.org/W2115448026","https://openalex.org/W2364596480"],"abstract_inverted_index":{"This":[0,23],"paper":[1,175],"presents":[2],"a":[3,32,48,79,92,159],"Built-In":[4],"Self-Test":[5],"(BIST)":[6],"scheme":[7,128],"to":[8,30],"measure":[9],"high":[10,104],"speed":[11],"double":[12],"data":[13,36],"rate":[14],"(DDR)":[15],"memory":[16,121],"output":[17,106,167,188],"timing":[18,80,87,108,189],"using":[19,47,146],"low":[20],"cost":[21],"testers.":[22],"technique":[24],"uses":[25],"an":[26],"on-chip":[27],"pattern":[28],"generator":[29],"generate":[31],"time":[33,42],"delay":[34,43],"between":[35],"and":[37,85,133,151,184],"data-strobe":[38],"or":[39],"clock.":[40],"The":[41,140],"is":[44,72,83,89,115],"controlled":[45],"precisely":[46],"phase":[49,63],"interpolator":[50],"based":[51],"cycle-by-cycle":[52],"control":[53],"method.":[54],"A":[55],"novel":[56],"method":[57],"for":[58,118,137,165],"testing":[59,119,166],"the":[60,76,86,95,135,138,147,170,177],"resolution":[61,161],"of":[62,94,162,179],"interpolator,":[64],"which":[65,114],"does":[66],"not":[67],"need":[68],"any":[69],"extra":[70],"hardware,":[71],"also":[73],"presented.":[74,156],"Using":[75,169],"test":[77,96,101,160,172],"resolution,":[78],"pass/fail":[81],"flag":[82],"set":[84],"margin":[88],"quantified":[90],"as":[91],"multiple":[93],"clock":[97],"cycle.":[98],"Since":[99],"these":[100,124],"results":[102,154],"have":[103],"observability,":[105],"per-pin":[107,182],"performance":[109],"can":[110],"be":[111],"diagnosed":[112],"easily,":[113],"especially":[116],"good":[117],"parallel":[120],"interfaces.":[122],"Moreover,":[123],"features":[125],"make":[126],"our":[127],"compatible":[129],"with":[130],"low-cost":[131],"testers":[132],"decreases":[134],"time-to-market":[136],"chip.":[139],"BIST":[141],"circuit":[142],"has":[143],"been":[144],"implemented":[145],"0.18-\u03bcm":[148],"CMOS":[149],"process,":[150],"chip":[152],"measurement":[153],"are":[155],"We":[157],"obtained":[158],"10":[163],"ps":[164],"timing.":[168],"fabricated":[171],"chip,":[173],"this":[174],"shows":[176],"effects":[178],"switching":[180],"noise,":[181],"skews":[183],"slew-rate":[185],"change":[186],"on":[187],"variations.":[190]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
