{"id":"https://openalex.org/W2102186636","doi":"https://doi.org/10.1109/vts.2011.5783781","title":"A new methodology for realistic open defect detection probability evaluation under process variations","display_name":"A new methodology for realistic open defect detection probability evaluation under process variations","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2102186636","doi":"https://doi.org/10.1109/vts.2011.5783781","mag":"2102186636"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2011.5783781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2011.5783781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"29th VLSI Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083880522","display_name":"Jesus Moreno","orcid":null},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"Jesus Moreno","raw_affiliation_strings":["Department of Electronic Engineering, National Institute for Astrophysics Optics and Electronics, Puebla, Mexico","Department of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics \u2013 INAOE, Puebla, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Institute for Astrophysics Optics and Electronics, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]},{"raw_affiliation_string":"Department of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics \u2013 INAOE, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038219219","display_name":"Victor Champac","orcid":"https://orcid.org/0000-0002-4440-3800"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Victor Champac","raw_affiliation_strings":["Department of Electronic Engineering, National Institute for Astrophysics Optics and Electronics, Puebla, Mexico","Department of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics \u2013 INAOE, Puebla, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Institute for Astrophysics Optics and Electronics, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]},{"raw_affiliation_string":"Department of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics \u2013 INAOE, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069159925","display_name":"M. Renovell","orcid":"https://orcid.org/0000-0002-3896-8231"},"institutions":[{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Michel Renovell","raw_affiliation_strings":["LIRMM, Universite de Montpellier II, Montpellier, France","LIRMM-Universite de Montpellier II, 161 rue Ada 34392, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Universite de Montpellier II, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM-Universite de Montpellier II, 161 rue Ada 34392, France","institution_ids":["https://openalex.org/I19894307"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5083880522"],"corresponding_institution_ids":["https://openalex.org/I39824353"],"apc_list":null,"apc_paid":null,"fwci":1.0074,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.7803551,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"184","last_page":"189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.695459246635437},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6407249569892883},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5647580027580261},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5610285401344299},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5094736218452454},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4967363476753235},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.46751075983047485},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46292659640312195},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.45996198058128357},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4271588921546936},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4107666611671448},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3788636326789856},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2751622498035431},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20128589868545532},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.11390349268913269},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11222261190414429}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.695459246635437},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6407249569892883},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5647580027580261},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5610285401344299},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5094736218452454},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4967363476753235},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.46751075983047485},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46292659640312195},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.45996198058128357},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4271588921546936},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4107666611671448},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3788636326789856},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2751622498035431},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20128589868545532},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.11390349268913269},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11222261190414429},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2011.5783781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2011.5783781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"29th VLSI Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321739","display_name":"Consejo Nacional de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/059ex5q34"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W164528542","https://openalex.org/W1491093261","https://openalex.org/W1515088817","https://openalex.org/W1667165204","https://openalex.org/W1727912659","https://openalex.org/W1735018384","https://openalex.org/W1958909498","https://openalex.org/W1974887607","https://openalex.org/W1975499858","https://openalex.org/W1991398325","https://openalex.org/W2008534549","https://openalex.org/W2046245205","https://openalex.org/W2049269261","https://openalex.org/W2090927611","https://openalex.org/W2137041591","https://openalex.org/W2137552141","https://openalex.org/W2144102158","https://openalex.org/W2157210245","https://openalex.org/W2160968649","https://openalex.org/W2169294720","https://openalex.org/W6606818822","https://openalex.org/W6629346665","https://openalex.org/W6634090017","https://openalex.org/W6644010781","https://openalex.org/W7024001005"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2014709025","https://openalex.org/W2155019192","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2170979950","https://openalex.org/W1900707063"],"abstract_inverted_index":{"CMOS":[0],"IC":[1],"scaling":[2],"has":[3],"provided":[4],"significant":[5],"improvements":[6],"in":[7,12,117],"electronic":[8],"circuit":[9],"performance.":[10],"Advances":[11],"test":[13,143,158],"methodologies":[14],"to":[15,99,121,145,161],"deal":[16],"with":[17,141],"new":[18],"failure":[19],"mechanisms":[20],"and":[21,47],"nanometer":[22,42],"issues":[23],"are":[24,28],"required.":[25],"Interconnect":[26],"opens":[27,129],"an":[29],"important":[30],"defect":[31,70],"mechanism":[32],"that":[33,71],"requires":[34],"detailed":[35],"knowledge":[36],"of":[37,52,67,83,92,109,125,127],"its":[38],"physical":[39],"properties.":[40],"In":[41,57],"process,":[43],"variability":[44,77],"is":[45,54,78,87,115],"predominant":[46],"considering":[48],"only":[49],"nominal":[50],"value":[51],"parameters":[53,82,94],"not":[55],"realistic.":[56],"this":[58],"work,":[59],"a":[60,64,118,142,156],"model":[61],"for":[62,95,130],"computing":[63],"realistic":[65],"coverage":[66],"via":[68,128],"open":[69],"takes":[72],"into":[73],"account":[74],"the":[75,84,93,100,107,110,123,151],"process":[76],"proposed.":[79],"Correlation":[80],"between":[81],"affected":[85],"gates":[86,97],"considered.":[88],"Furthermore,":[89],"spatial":[90],"correlation":[91],"those":[96],"tied":[98],"defective":[101],"floating":[102],"node":[103],"can":[104,154],"also":[105],"influence":[106],"detectability":[108],"defect.":[111],"The":[112,135],"proposed":[113,136],"methodology":[114,144],"implemented":[116],"software":[119],"tool":[120],"determine":[122],"probability":[124,138],"detection":[126,137],"some":[131],"ISCAS":[132],"benchmark":[133],"circuits.":[134],"evaluation":[139],"together":[140],"generate":[146],"favorable":[147],"logic":[148],"conditions":[149],"at":[150],"coupling":[152],"lines":[153],"allow":[155],"better":[157],"quality":[159],"leading":[160],"higher":[162],"product":[163],"reliability.":[164]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}