{"id":"https://openalex.org/W2106315190","doi":"https://doi.org/10.1109/vts.2011.5783761","title":"Efficient and product-representative timing model validation","display_name":"Efficient and product-representative timing model validation","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2106315190","doi":"https://doi.org/10.1109/vts.2011.5783761","mag":"2106315190"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2011.5783761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2011.5783761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"29th VLSI Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021724906","display_name":"Eun Jung Jang","orcid":"https://orcid.org/0000-0002-9104-5129"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eun Jung Jang","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, USA","Computer Engineering Research Center, The University of Texas Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Computer Engineering Research Center, The University of Texas Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026865205","display_name":"Anne Gattiker","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anne Gattiker","raw_affiliation_strings":["Austin Research Laboratory, IBM, Austin, TX, USA","Austin Research Lab, IBM, TX 78758, USA"],"affiliations":[{"raw_affiliation_string":"Austin Research Laboratory, IBM, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"Austin Research Lab, IBM, TX 78758, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046886936","display_name":"Sani Nassif","orcid":"https://orcid.org/0000-0002-5096-4794"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sani Nassif","raw_affiliation_strings":["Austin Research Laboratory, IBM, Austin, TX, USA","Austin Research Lab, IBM, TX 78758, USA"],"affiliations":[{"raw_affiliation_string":"Austin Research Laboratory, IBM, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"Austin Research Lab, IBM, TX 78758, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jacob A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, USA","Computer Engineering Research Center, The University of Texas Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Computer Engineering Research Center, The University of Texas Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5021724906"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":1.2884,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.81769634,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6955410242080688},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6169252395629883},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5676878094673157},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5082797408103943},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4598762094974518},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.44208648800849915},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38118696212768555},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27028322219848633},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23405444622039795},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.20339539647102356},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15117621421813965},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.1507936716079712}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6955410242080688},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6169252395629883},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5676878094673157},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5082797408103943},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4598762094974518},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.44208648800849915},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38118696212768555},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27028322219848633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23405444622039795},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.20339539647102356},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15117621421813965},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.1507936716079712},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2011.5783761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2011.5783761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"29th VLSI Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1583788531","https://openalex.org/W1979194489","https://openalex.org/W2010430894","https://openalex.org/W2031804358","https://openalex.org/W2104949917","https://openalex.org/W2120719803","https://openalex.org/W2121783291","https://openalex.org/W2126693329","https://openalex.org/W2129267471","https://openalex.org/W2155636448","https://openalex.org/W2157111192","https://openalex.org/W2168812909","https://openalex.org/W2187401169","https://openalex.org/W3014502717","https://openalex.org/W3140757139","https://openalex.org/W4249020130","https://openalex.org/W4252110273","https://openalex.org/W4285719527","https://openalex.org/W6678797189","https://openalex.org/W6679301951","https://openalex.org/W6683159444","https://openalex.org/W6686498681"],"related_works":["https://openalex.org/W2110367374","https://openalex.org/W3151506308","https://openalex.org/W2107108222","https://openalex.org/W2794688131","https://openalex.org/W2136310485","https://openalex.org/W1966046150","https://openalex.org/W4234370441","https://openalex.org/W2373135325","https://openalex.org/W4388667102","https://openalex.org/W2080035745"],"abstract_inverted_index":{"Timing":[0],"analysis":[1],"is":[2,73,175,198,206],"a":[3,70,145,160,229,240,266],"key":[4],"sign-off":[5],"step":[6],"in":[7,65,79,104,239,247],"the":[8,58,142,172,188,233,248],"design":[9],"of":[10,115,144,150,159,177,217],"today's":[11],"chips,":[12],"but":[13,94,186],"as":[14,39],"technology":[15],"advances,":[16],"it":[17,45,72],"becomes":[18],"ever":[19],"more":[20],"challenging":[21],"to":[22,48,75,83,123,208],"create":[23],"timing":[24,59,77,85,151],"models":[25,51,78,86],"that":[26,55,61,111,179,196,231,243,253],"accurately":[27,56],"reflect":[28],"real":[29,116],"timing-related":[30],"behavior.":[31],"Complex":[32],"dependencies":[33],"on":[34],"second":[35],"order":[36],"phenomena,":[37],"such":[38],"pattern":[40],"density":[41],"and":[42,52,107,125,163,183,200],"stress/strain":[43],"make":[44],"very":[46],"difficult":[47],"develop":[49],"device":[50],"simulation":[53],"tools":[54],"predict":[57],"behavior":[60],"will":[62],"be":[63,121,257],"seen":[64],"actual":[66],"product":[67],"silicon.":[68,80],"As":[69],"result,":[71],"necessary":[74],"validate":[76,84],"Traditional":[81],"ways":[82],"use":[87],"ring":[88,161],"oscillators":[89,101],"or":[90],"perform":[91],"delay":[92,130,165,203,234],"testing":[93,166],"both":[95],"approaches":[96],"have":[97],"significant":[98],"drawbacks.":[99],"Ring":[100],"lack":[102],"diversity":[103],"circuit":[105],"structure":[106,174],"present":[108],"layout":[109],"configurations":[110],"are":[112,180,222],"not":[113,132],"typical":[114],"products.":[117],"Delay":[118],"test":[119,147,173,191,204,210],"can":[120,256],"expensive":[122],"apply":[124],"provides":[126],"directly":[127],"only":[128],"path":[129,164,218,226,238],"information":[131],"individual":[133],"gate":[134,263],"delays.":[135,219],"To":[136],"address":[137],"these":[138],"limitations,":[139],"we":[140],"explore":[141],"potential":[143],"new":[146],"structure-based":[148],"method":[149],"model":[152],"validation.":[153],"The":[154],"proposed":[155],"approach":[156],"combines":[157],"benefits":[158],"oscillator":[162],"while":[167],"addressing":[168],"their":[169],"limitations.":[170],"Specifically,":[171],"composed":[176],"circuits":[178],"physically":[181],"synthesized":[182],"therefore":[184],"product-representative,":[185],"configures":[187],"devices":[189],"under":[190,259],"into":[192],"oscillating":[193],"paths":[194],"so":[195],"measurement":[197],"easy":[199],"inexpensive.":[201],"Path":[202],"ATPG":[205],"used":[207],"generate":[209],"patterns":[211],"whose":[212],"oscillation":[213],"frequencies":[214],"provide":[215],"measures":[216],"Gate":[220],"delays":[221,227],"deduced":[223],"from":[224],"those":[225],"using":[228,265],"matrix":[230,249],"codes":[232],"elements":[235],"comprising":[236],"each":[237],"careful":[241],"way":[242],"overcomes":[244],"overdetermination":[245],"problems":[246],"algebra.":[250],"Results":[251],"show":[252],"RMS":[254],"errors":[255],"maintained":[258],"5%":[260],"for":[261],"all":[262],"types":[264],"chosen":[267],"circuit.":[268]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}