{"id":"https://openalex.org/W1981661855","doi":"https://doi.org/10.1109/vts.2010.5469591","title":"Theoretical analysis for low-power test decompression using test-slice duplication","display_name":"Theoretical analysis for low-power test decompression using test-slice duplication","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W1981661855","doi":"https://doi.org/10.1109/vts.2010.5469591","mag":"1981661855"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2010.5469591","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112638273","display_name":"Szu-Pang Mu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Szu-Pang Mu","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering; National Chiao Tung University; Hsinchu Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering; National Chiao Tung University; Hsinchu Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045156360","display_name":"Mango C.-T. Chao","orcid":"https://orcid.org/0000-0002-7299-9015"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mango C.-T. Chao","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Department of Electronics Engineering; National Chiao Tung University; Hsinchu Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Electronics Engineering; National Chiao Tung University; Hsinchu Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.7018,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.65960216,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9837999939918518,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.750895619392395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6845336556434631},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5972076058387756},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5655239224433899},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5580675601959229},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5125317573547363},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4335312843322754},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.432405561208725},{"id":"https://openalex.org/keywords/volume","display_name":"Volume (thermodynamics)","score":0.43085676431655884},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4223906397819519},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.41241782903671265},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2769744396209717},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15376335382461548},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14745181798934937},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12839677929878235}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.750895619392395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6845336556434631},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5972076058387756},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5655239224433899},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5580675601959229},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5125317573547363},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4335312843322754},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.432405561208725},{"id":"https://openalex.org/C20556612","wikidata":"https://www.wikidata.org/wiki/Q4469374","display_name":"Volume (thermodynamics)","level":2,"score":0.43085676431655884},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4223906397819519},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.41241782903671265},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2769744396209717},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15376335382461548},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14745181798934937},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12839677929878235},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2010.5469591","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1528223898","https://openalex.org/W1561466126","https://openalex.org/W1966348745","https://openalex.org/W2046352832","https://openalex.org/W2080510479","https://openalex.org/W2099337863","https://openalex.org/W2099767695","https://openalex.org/W2101900253","https://openalex.org/W2105028194","https://openalex.org/W2110232289","https://openalex.org/W2118922141","https://openalex.org/W2119691242","https://openalex.org/W2122955150","https://openalex.org/W2131803874","https://openalex.org/W2132881562","https://openalex.org/W2135547345","https://openalex.org/W2136567303","https://openalex.org/W2139234345","https://openalex.org/W2144033909","https://openalex.org/W2147326666","https://openalex.org/W2160621850","https://openalex.org/W2166163625","https://openalex.org/W2169839635","https://openalex.org/W2169854732","https://openalex.org/W3141221995","https://openalex.org/W4229598199","https://openalex.org/W4249647124","https://openalex.org/W6641769569","https://openalex.org/W6674662139","https://openalex.org/W6675185978","https://openalex.org/W6681008240"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2147986372","https://openalex.org/W2786111245","https://openalex.org/W1979305473","https://openalex.org/W3009953521","https://openalex.org/W4234763172","https://openalex.org/W2992024382","https://openalex.org/W2125317684","https://openalex.org/W1606802855","https://openalex.org/W3121464923"],"abstract_inverted_index":{"This":[0],"paper":[1,54],"presents":[2],"a":[3,44,89],"single-test-input":[4],"test-decompression":[5],"scheme,":[6,68],"named":[7],"STSD,":[8],"which":[9],"utilize":[10],"the":[11,18,24,38,57,79,105,108,113],"technique":[12],"of":[13,32,40,82,86,107,115],"test-slice":[14,45],"duplication":[15],"to":[16,55,76],"reduce":[17],"test-data":[19],"volume":[20],"as":[21,23],"well":[22],"signal":[25],"transitions":[26,64],"along":[27],"scan":[28],"paths.":[29],"The":[30,93],"encoding":[31],"STSD":[33,67,83,117],"scheme":[34,84],"focuses":[35],"on":[36,97],"maximizing":[37],"number":[39],"duplications":[41],"made":[42],"by":[43,66],"template.":[46],"Mathematical":[47],"models":[48,111],"are":[49],"also":[50],"developed":[51],"in":[52,70],"this":[53],"estimate":[56],"compression":[58],"ratio,":[59],"test-application":[60],"time,":[61],"and":[62,69,100,112],"scan-in":[63],"caused":[65],"turn":[71],"can":[72],"further":[73],"help":[74],"designers":[75],"efficiently":[77],"identify":[78],"best":[80],"configuration":[81],"instead":[85],"going":[87],"through":[88],"time-consuming":[90],"simulation":[91],"process.":[92],"experimental":[94],"results":[95],"based":[96],"large":[98],"ISCAS":[99],"ITC":[101],"benchmark":[102],"circuits":[103],"demonstrate":[104],"accuracy":[106],"proposed":[109],"mathematical":[110],"advantages":[114],"using":[116],"scheme.":[118]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}