{"id":"https://openalex.org/W2033206049","doi":"https://doi.org/10.1109/vts.2010.5469564","title":"High level synthesis of a Front End filter and DSP engine for analog to digital conversion &amp;#x2013; a case study","display_name":"High level synthesis of a Front End filter and DSP engine for analog to digital conversion &amp;#x2013; a case study","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2033206049","doi":"https://doi.org/10.1109/vts.2010.5469564","mag":"2033206049"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2010.5469564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039174773","display_name":"Jose G. Mena","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jose G. Mena","raw_affiliation_strings":["Freescale Semiconductor Inc, Austin, TX, US","Freescale Semiconductor Inc"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc, Austin, TX, US","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055618501","display_name":"Richard Deken","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Richard Deken","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA","Freescale Semiconductor Inc"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027551230","display_name":"James E. Coker","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"James E. Coker","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA","Freescale Semiconductor Inc"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109145154","display_name":"Mark S Johnstone","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mark S Johnstone","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA","Freescale Semiconductor Inc"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003187503","display_name":"Sergio R. Ramirez","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sergio R. Ramirez","raw_affiliation_strings":["(Cadence Design Systems Inc.)","Cadence Design Systems Inc"],"affiliations":[{"raw_affiliation_string":"(Cadence Design Systems Inc.)","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010525213","display_name":"Peter W. Frey","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Frey","raw_affiliation_strings":["Cadence Design Systems, Inc., USA","Cadence Design Systems Inc"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5039174773"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.11517183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"252","last_page":"252"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7138751745223999},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6152985095977783},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.569709837436676},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5675268173217773},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5327646136283875},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.48658525943756104},{"id":"https://openalex.org/keywords/digital-down-converter","display_name":"Digital down converter","score":0.47714897990226746},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4125722348690033},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3548746705055237},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.29460883140563965},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.22902053594589233},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20175763964653015},{"id":"https://openalex.org/keywords/digital-signal","display_name":"Digital signal","score":0.17482346296310425},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14086374640464783}],"concepts":[{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7138751745223999},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6152985095977783},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.569709837436676},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5675268173217773},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5327646136283875},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.48658525943756104},{"id":"https://openalex.org/C99167442","wikidata":"https://www.wikidata.org/wiki/Q559292","display_name":"Digital down converter","level":4,"score":0.47714897990226746},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4125722348690033},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3548746705055237},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29460883140563965},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22902053594589233},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20175763964653015},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.17482346296310425},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14086374640464783}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2010.5469564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4289538008","https://openalex.org/W3186427148","https://openalex.org/W2138282914","https://openalex.org/W2427933582","https://openalex.org/W3179449891","https://openalex.org/W4231274081","https://openalex.org/W2531450434","https://openalex.org/W2025879119","https://openalex.org/W4254884584","https://openalex.org/W2074881760"],"abstract_inverted_index":{"We":[0],"present":[1],"the":[2,30,50],"design":[3],"of":[4,10],"a":[5,11],"Sinc":[6],"Cubed":[7],"Decimator":[8],"and":[9,29,42],"Front":[12],"End":[13],"DSP":[14],"Engine":[15],"for":[16],"Analog":[17],"to":[18,38],"Digital":[19],"Conversion":[20],"using":[21],"high-level":[22],"synthesis.":[23],"The":[24],"input":[25],"language":[26],"was":[27,35],"SystemC":[28],"High":[31],"Level":[32],"Synthesis":[33],"tool":[34],"Cadence's":[36],"C":[37],"Silicon":[39],"compiler.":[40],"Area":[41],"timing":[43],"results,":[44],"as":[45,47],"well":[46],"comments":[48],"on":[49],"overall":[51],"experience,":[52],"are":[53],"also":[54],"presented.":[55]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
