{"id":"https://openalex.org/W2117796765","doi":"https://doi.org/10.1109/vts.2002.1011172","title":"Validation and test of network processors and ASICs","display_name":"Validation and test of network processors and ASICs","publication_year":2005,"publication_date":"2005-08-25","ids":{"openalex":"https://openalex.org/W2117796765","doi":"https://doi.org/10.1109/vts.2002.1011172","mag":"2117796765"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2002.1011172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004658137","display_name":"Faraydon Karim","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Karim","raw_affiliation_strings":["STMicroelectronics, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087237429","display_name":"H. Konuk","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127325","display_name":"Broadcom (United States)","ror":"https://ror.org/035gt5s03","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127325"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Konuk","raw_affiliation_strings":["Broadcom, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Broadcom, USA","institution_ids":["https://openalex.org/I4210127325"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Keesup Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keesup Kim","raw_affiliation_strings":["Intel Corporation, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025308099","display_name":"S. Dey","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Dey","raw_affiliation_strings":["University of California, San Diego, San Diego, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, San Diego, San Diego, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1852286,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"407","last_page":"407"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.769927978515625},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.6459840536117554},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6333050727844238},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4844975173473358},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.48319852352142334},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47917380928993225},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4580598771572113},{"id":"https://openalex.org/keywords/networking-hardware","display_name":"Networking hardware","score":0.4506995975971222},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3383883833885193},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3143174946308136},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.2762048840522766}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.769927978515625},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.6459840536117554},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6333050727844238},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4844975173473358},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.48319852352142334},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47917380928993225},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4580598771572113},{"id":"https://openalex.org/C159631557","wikidata":"https://www.wikidata.org/wiki/Q1546066","display_name":"Networking hardware","level":2,"score":0.4506995975971222},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3383883833885193},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3143174946308136},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.2762048840522766},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2002.1011172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4395090620","https://openalex.org/W2290315036","https://openalex.org/W1828239946","https://openalex.org/W3142211975","https://openalex.org/W1974983535","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W2015261377"],"abstract_inverted_index":{"Rapid":[0],"growth":[1],"in":[2,74,177,232,242,272],"the":[3,21,53,79,117,141,148,155,174,237,283,290,326,341],"internet":[4],"and":[5,13,20,26,31,47,58,62,69,104,108,119,136,197,207,217,252,263,304],"enterprise":[6],"network":[7,45,56,67,85,126,167,183,250],"traffic,":[8],"need":[9,222,300],"by":[10],"both":[11],"subscribers":[12],"operators":[14],"to":[15,35,131,139,153,223,280,301,306,323],"provide":[16,154],"for":[17,39],"differentiated":[18],"services,":[19],"constant":[22],"evolution":[23],"of":[24,55,81,93,123,150,164,194,239,334,340],"wireline":[25],"wireless":[27],"networking":[28],"functions,":[29],"algorithms":[30],"standards,":[32],"is":[33],"leading":[34],"a":[36,82,88,105,179,318],"high":[37,41,199],"demand":[38],"ultra":[40],"speed,":[42,144],"yet":[43],"programmable,":[44],"processors":[46,68,152],"ASICs.":[48,70],"This":[49],"session":[50,76,234],"will":[51,77,115,161,172,214,226,235,286,295,316],"introduce":[52],"design":[54],"processors,":[57,95,192],"highlight":[59],"important":[60],"validation":[61,118],"test":[63,121,212,219,327],"challenges":[64,175,220,271],"associated":[65],"with":[66,308,325],"The":[71,113,158,229,293],"first":[72],"speaker":[73],"this":[75,233],"review":[78],"architecture":[80,134],"typical":[83],"OC-192":[84],"processor":[86,127,184],"\u2013":[87],"highly":[89,106],"complex":[90,109],"system-on-chip,":[91],"consisting":[92],"multiple":[94,99,151,198,257,266],"specialized":[96],"hardware":[97],"blocks,":[98,202],"high-speed":[100,181],"embedded":[101,165],"memory":[102,209],"units,":[103],"concurrent":[107],"on-chip":[110],"interconnect":[111],"structure.":[112],"talk":[114,160,231,294],"analyze":[116],"manufacturing":[120],"problems":[122],"hardware-software":[124],"GHz":[125,166],"chips,":[128],"which":[129,186],"have":[130],"use":[132],"aggressive":[133],"designs":[135],"nano-meter":[137],"technologies":[138],"obtain":[140],"required":[142],"multi-GHz":[143],"while":[145],"relying":[146],"on":[147],"presence":[149],"necessary":[156],"flexibility.":[157],"second":[159],"address":[162,236],"testing":[163,178,241,274],"processors.":[168],"In":[169,245],"particular,":[170],"it":[171,276],"describe":[173],"faced":[176],"specific":[180],"low-power":[182],"chip,":[185],"includes":[187],"two":[188],"custom-design":[189],"64-bit":[190],"MIPS":[191],"0.5MB":[193],"L2":[195],"cache,":[196],"speed":[200],"communication":[201,246],"such":[203,248],"as":[204,249],"gigabit-ethernet,":[205],"hypertransport,":[206],"double-data-rate":[208],"controllers.":[210],"Some":[211],"solutions":[213],"be":[215,224,227,302],"presented,":[216],"major":[218],"that":[221],"addressed":[225],"listed.":[228],"third":[230],"problem":[238,311],"delay":[240,298,335],"communications":[243],"chips.":[244],"devices":[247],"switches":[251],"routers,":[253],"there":[254],"usually":[255],"are":[256],"unrelated":[258],"clocks":[259],"controlling":[260],"various":[261],"interfaces":[262],"logic.":[264],"These":[265],"clock":[267],"domains":[268],"presents":[269],"unique":[270],"production":[273,313],"since":[275],"becomes":[277],"very":[278],"difficult":[279],"predict":[281],"when":[282],"expected":[284],"output":[285],"show":[287,296],"up":[288],"at":[289],"pin":[291],"boundary.":[292],"why":[297],"defects":[299],"addressed,":[303],"how":[305],"deal":[307,324],"cycle":[309],"uncertainty":[310],"during":[312],"testing.":[314],"It":[315],"present":[317],"novel":[319],"compaction":[320],"technique":[321],"used":[322],"data":[328],"volume":[329],"explosion":[330],"resulting":[331],"from":[332],"including":[333],"defect":[336],"screening":[337],"tests.":[338],"Proceedings":[339],"20":[342],"th":[343],"IEEE":[344,353],"VLSI":[345],"Test":[346],"Symposium":[347],"(VTS\u009202)":[348],"1093-0167/02":[349],"$17.00":[350],"\u00a9":[351],"2002":[352]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}