{"id":"https://openalex.org/W2113435641","doi":"https://doi.org/10.1109/vts.2002.1011161","title":"A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits","display_name":"A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2113435641","doi":"https://doi.org/10.1109/vts.2002.1011161","mag":"2113435641"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2002.1011161","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011161","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040112008","display_name":"T. Hosokawa","orcid":"https://orcid.org/0000-0001-7923-1781"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Hosokawa","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071175870","display_name":"Hiroshi Date","orcid":"https://orcid.org/0000-0001-7262-6000"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Date","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113741180","display_name":"Michiaki Muraoka","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Muraoka","raw_affiliation_strings":["Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology Development Department, Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":[]},{"raw_affiliation_string":"Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"328","last_page":"335"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.750742495059967},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.7490757703781128},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.7174756526947021},{"id":"https://openalex.org/keywords/test-plan","display_name":"Test plan","score":0.689117431640625},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6624009609222412},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5926886796951294},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.5791621804237366},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5715267658233643},{"id":"https://openalex.org/keywords/plan","display_name":"Plan (archaeology)","score":0.4391764998435974},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.4371856153011322},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.42613571882247925},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4234412908554077},{"id":"https://openalex.org/keywords/test-management-approach","display_name":"Test Management Approach","score":0.41420865058898926},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37654319405555725},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3638923466205597},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.29691702127456665},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23725169897079468},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.19561812281608582},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1205233633518219},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10209712386131287},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.07098555564880371}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.750742495059967},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.7490757703781128},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.7174756526947021},{"id":"https://openalex.org/C12148698","wikidata":"https://www.wikidata.org/wiki/Q364651","display_name":"Test plan","level":3,"score":0.689117431640625},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6624009609222412},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5926886796951294},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.5791621804237366},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5715267658233643},{"id":"https://openalex.org/C2776505523","wikidata":"https://www.wikidata.org/wiki/Q4785468","display_name":"Plan (archaeology)","level":2,"score":0.4391764998435974},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.4371856153011322},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.42613571882247925},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4234412908554077},{"id":"https://openalex.org/C7435765","wikidata":"https://www.wikidata.org/wiki/Q7705776","display_name":"Test Management Approach","level":5,"score":0.41420865058898926},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37654319405555725},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3638923466205597},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.29691702127456665},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23725169897079468},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.19561812281608582},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1205233633518219},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10209712386131287},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.07098555564880371},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C173291955","wikidata":"https://www.wikidata.org/wiki/Q732332","display_name":"Weibull distribution","level":2,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2002.1011161","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011161","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1483338234","https://openalex.org/W1554885925","https://openalex.org/W1837475237","https://openalex.org/W1855007419","https://openalex.org/W1939659579","https://openalex.org/W2054781056","https://openalex.org/W2098427313","https://openalex.org/W2133745968","https://openalex.org/W2147556474","https://openalex.org/W2155341318","https://openalex.org/W4231816245","https://openalex.org/W4302084786","https://openalex.org/W4302458519","https://openalex.org/W6633069435","https://openalex.org/W6674967428"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2543176856","https://openalex.org/W2157212570","https://openalex.org/W3088373974","https://openalex.org/W2149211345","https://openalex.org/W2624668974","https://openalex.org/W2806771822","https://openalex.org/W4230966676","https://openalex.org/W2799101079","https://openalex.org/W2111803469"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,8,13,18,37,41],"test":[4,10,14,20,32,43,54,67],"generation":[5,15,46,68],"method":[6,16],"using":[7,17],"compacted":[9,19,42],"table":[11,22,45],"and":[12],"plan":[21,44],"for":[23,40,56],"RTL":[24,58],"data":[25,59],"path":[26,60],"circuits":[27,61],"with":[28,63],"DFT":[29],"where":[30],"hierarchical":[31,66],"generations":[33],"are":[34],"applicable.":[35],"Moreover,":[36],"heuristic":[38],"algorithm":[39],"is":[47],"proposed.":[48],"The":[49],"proposed":[50],"methods":[51],"could":[52],"shorten":[53],"lengths":[55],"some":[57],"compared":[62],"the":[64],"conventional":[65],"method.":[69]},"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}