{"id":"https://openalex.org/W2107291559","doi":"https://doi.org/10.1109/vts.2002.1011144","title":"Program slicing for hierarchical test generation","display_name":"Program slicing for hierarchical test generation","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2107291559","doi":"https://doi.org/10.1109/vts.2002.1011144","mag":"2107291559"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2002.1011144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112274608","display_name":"V.M. Vedula","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V.M. Vedula","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108522396","display_name":"J. Bhadra","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Bhadra","raw_affiliation_strings":["Somerset PowerPC Design Center, Motorola, Inc., Austin, TX, USA","Motorola"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Somerset PowerPC Design Center, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]},{"raw_affiliation_string":"Motorola","institution_ids":["https://openalex.org/I1333370159"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"237","last_page":"243"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8171419501304626},{"id":"https://openalex.org/keywords/program-slicing","display_name":"Program slicing","score":0.8142353296279907},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7927979826927185},{"id":"https://openalex.org/keywords/slicing","display_name":"Slicing","score":0.7879807353019714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7606544494628906},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5553501844406128},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5143665075302124},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.46450066566467285},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.45425912737846375},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.45233580470085144},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4484618902206421},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4194656312465668},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.41692185401916504},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38826891779899597},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3872295022010803},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3561710715293884},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.339563250541687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.27199244499206543},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24776235222816467},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21311205625534058},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1935485601425171},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12421068549156189},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.0794340968132019}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8171419501304626},{"id":"https://openalex.org/C91071405","wikidata":"https://www.wikidata.org/wiki/Q1413145","display_name":"Program slicing","level":3,"score":0.8142353296279907},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7927979826927185},{"id":"https://openalex.org/C2776190703","wikidata":"https://www.wikidata.org/wiki/Q488148","display_name":"Slicing","level":2,"score":0.7879807353019714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7606544494628906},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5553501844406128},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5143665075302124},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.46450066566467285},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.45425912737846375},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.45233580470085144},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4484618902206421},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4194656312465668},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.41692185401916504},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38826891779899597},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3872295022010803},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3561710715293884},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.339563250541687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27199244499206543},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24776235222816467},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21311205625534058},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1935485601425171},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12421068549156189},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0794340968132019},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2002.1011144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310620","display_name":"University of Texas at Austin","ror":"https://ror.org/00hj54h04"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1522479539","https://openalex.org/W1559507652","https://openalex.org/W1876406499","https://openalex.org/W2000320538","https://openalex.org/W2051907727","https://openalex.org/W2104879512","https://openalex.org/W2114676663","https://openalex.org/W2135129887","https://openalex.org/W2147449017","https://openalex.org/W2158439616","https://openalex.org/W2159436237","https://openalex.org/W2162046779","https://openalex.org/W2162310108","https://openalex.org/W2252806406","https://openalex.org/W2293624369","https://openalex.org/W3143014988","https://openalex.org/W4250822128","https://openalex.org/W6631279040","https://openalex.org/W6681899058"],"related_works":["https://openalex.org/W2189059878","https://openalex.org/W1994765499","https://openalex.org/W1679970298","https://openalex.org/W2140497172","https://openalex.org/W1876049804","https://openalex.org/W1827781850","https://openalex.org/W1570685651","https://openalex.org/W2489638043","https://openalex.org/W2168652618","https://openalex.org/W4246649969"],"abstract_inverted_index":{"Sequential":[0],"Automatic":[1],"Test":[2,59],"Pattern":[3],"Generation":[4],"(ATPG)":[5],"is":[6,64],"extremely":[7],"computation":[8],"intensive":[9],"and":[10,40,82],"produces":[11],"good":[12],"results":[13,83],"only":[14],"on":[15,27,84],"relatively":[16],"small":[17],"designs.":[18],"This":[19],"paper":[20],"develops":[21],"an":[22,74],"elegant":[23],"theoretical":[24],"basis,":[25],"based":[26],"program":[28],"slicing,":[29],"for":[30,49,54,77],"hierarchical":[31],"ATPG":[32],"which":[33],"targets":[34],"one":[35],"module":[36],"at":[37],"a":[38,51,62],"time":[39],"abstracts":[41],"the":[42,45,89,93],"rest":[43],"of":[44,92],"design.":[46],"The":[47,68],"technique":[48,69],"obtaining":[50],"\"constraint":[52],"slice\"":[53],"each":[55],"embedded":[56],"Module":[57],"Under":[58],"(MUT)":[60],"within":[61],"design":[63],"described":[65,79],"in":[66,73,80],"detail.":[67],"has":[70],"been":[71],"incorporated":[72],"automated":[75],"tool":[76],"designs":[78],"Verilog,":[81],"large":[85],"benchmark":[86],"circuits":[87],"show":[88],"significant":[90],"benefits":[91],"approach.":[94]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}