{"id":"https://openalex.org/W2123048423","doi":"https://doi.org/10.1109/vts.2002.1011123","title":"A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?","display_name":"A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?","publication_year":2002,"publication_date":"2002-01-01","ids":{"openalex":"https://openalex.org/W2123048423","doi":"https://doi.org/10.1109/vts.2002.1011123","mag":"2123048423"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2002.1011123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017819440","display_name":"Lee Song","orcid":null},"institutions":[{"id":"https://openalex.org/I22113271","display_name":"Teradyne (United States)","ror":"https://ror.org/02b00gr50","country_code":"US","type":"company","lineage":["https://openalex.org/I22113271"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Lee Song","raw_affiliation_strings":["Teradyne","TERADYNE"],"affiliations":[{"raw_affiliation_string":"Teradyne","institution_ids":["https://openalex.org/I22113271"]},{"raw_affiliation_string":"TERADYNE","institution_ids":["https://openalex.org/I22113271"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053110488","display_name":"P. Patton","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Patton","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5018075561","display_name":"W. Radermacher","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"W. Radermacher","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5017819440"],"corresponding_institution_ids":["https://openalex.org/I22113271"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1966267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11301","display_name":"Advanced Surface Polishing Techniques","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/semiconductor-industry","display_name":"Semiconductor industry","score":0.553936779499054},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.49934840202331543},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.43569260835647583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4139252305030823},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4134826958179474},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.37755367159843445},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3594781160354614},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2813003659248352},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2695292830467224},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.19980216026306152}],"concepts":[{"id":"https://openalex.org/C2987888538","wikidata":"https://www.wikidata.org/wiki/Q2986369","display_name":"Semiconductor industry","level":2,"score":0.553936779499054},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.49934840202331543},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.43569260835647583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4139252305030823},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4134826958179474},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.37755367159843445},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3594781160354614},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2813003659248352},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2695292830467224},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.19980216026306152},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2002.1011123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2002.1011123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1901574727","https://openalex.org/W1849410037","https://openalex.org/W1901848760","https://openalex.org/W2147058628","https://openalex.org/W2113707299","https://openalex.org/W2065005513","https://openalex.org/W2118869825","https://openalex.org/W2334559518","https://openalex.org/W1936555410","https://openalex.org/W2049073187"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given,":[3],"as":[4,33,95],"follows.":[5],"For":[6],"many":[7],"years,":[8],"the":[9,15,48,81,92,111,142,152,159,165,179,186,193,218,227,234,240,244,277,286,304,345],"semiconductor":[10],"industry":[11,112,228,316],"has":[12,45,181,229],"been":[13,174,182,230],"predicting":[14],"emergence":[16,153],"of":[17,25,62,125,134,146,154,185,223,236,248,271,288,306,318,338],"DFT":[18,30,42,54,74,148,215,237,249,260,272,297,307,319,326],"tester":[19,43,55,75,261,298],"market,":[20],"enabled":[21],"by":[22,196,239,342],"increasing":[23,132],"number":[24],"devices":[26,251],"being":[27],"designed":[28],"with":[29,131],"methodologies":[31],"such":[32,94],"scan":[34],"and":[35,58,102,117,212,309],"BIST.":[36],"The":[37,122,221,266],"search":[38],"for":[39,52,201],"low":[40,213],"cost":[41,214],"solutions":[44],"resulted":[46],"in":[47,56,65,86,91,97,169,199,226,233,250,280,296,334,344],"first":[49],"ITRS":[50],"roadmap":[51,64],"a":[53,59,73,202,259],"1999":[57],"major":[60],"revision":[61],"this":[63,224,281],"2001.":[66],"While":[67],"it":[68],"is":[69,252,268,285],"generally":[70],"understood":[71],"that":[72,206,246,258,291,301,312],"can":[76,207,274],"be":[77,109,330],"used":[78],"to":[79,163,178,256],"limit":[80],"digital":[82],"test":[83,120],"performance":[84,119,211],"envelope":[85],"production":[87],"testing,":[88],"some":[89,343],"trends":[90],"industry,":[93],"increase":[96],"mixed":[98,127,135],"signal":[99,128,136],"SOC":[100,137],"designs":[101],"multi":[103],"GHz":[104],"serial":[105],"IO":[106],"interfaces,":[107],"may":[108,139,302,313],"pushing":[110],"toward":[113],"more":[114],"highly":[115],"configurable":[116],"higher":[118],"solutions.":[121],"relative":[123,231],"immaturity":[124],"analog":[126],"DFT,":[129],"coupled":[130],"proliferation":[133],"devices,":[138],"also":[140],"prevent":[141],"wholesale":[143],"industry-wide":[144],"adoption":[145,247,317],"digital-only":[147],"testers.":[149,320],"In":[150],"addition,":[151],"novel":[155],"fault":[156],"models,":[157],"beyond":[158],"traditional":[160],"SSA":[161],"model,":[162],"cover":[164],"emerging":[166],"defects":[167],"found":[168],"advanced":[170],"silicon":[171],"technologies":[172],"have":[173],"noticeably":[175],"lacking.":[176],"Adding":[177],"fire":[180],"continuing":[183,253],"discussion":[184],"now":[187],"famous":[188],"$200/pin":[189],"tester,":[190],"which":[191],"highlights":[192],"pressure":[194],"faced":[195],"ATE":[197,241,335],"companies":[198],"looking":[200],"viable":[203],"business":[204],"model":[205],"provide":[208],"both":[209],"high":[210],"testers":[216,238,273,327],"at":[217],"same":[219],"time.":[220],"result":[222],"cloudiness":[225],"slowness":[232],"development":[235],"industry.":[242,346],"However,":[243],"fact":[245],"leads":[254],"us":[255],"believe":[257],"market":[262],"will":[263,292,328],"emerge":[264],"eventually.":[265],"question":[267],"what":[269],"kinds":[270],"best":[275],"exploit":[276],"opportunities":[278],"presented":[279],"cloudy":[282],"market.":[283],"This":[284,321],"second":[287],"two":[289],"sessions":[290],"explore":[293],"various":[294],"approaches":[295],"development,":[299],"features":[300],"determine":[303],"success":[305],"testers,":[308],"potential":[310],"catalysts":[311],"cause":[314],"wide-scale":[315],"session":[322],"explores":[323],"whether":[324],"successful":[325],"just":[329],"next":[331],"logical":[332],"steps":[333],"evolution":[336],"instead":[337],"radical":[339],"revolution":[340],"expected":[341]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
