{"id":"https://openalex.org/W2095626533","doi":"https://doi.org/10.1109/vtest.2004.1299250","title":"Memory BIST using ESP","display_name":"Memory BIST using ESP","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2095626533","doi":"https://doi.org/10.1109/vtest.2004.1299250","mag":"2095626533"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.2004.1299250","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2004.1299250","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd IEEE VLSI Test Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056383449","display_name":"Xiaogang Du","orcid":"https://orcid.org/0000-0002-0612-6064"},"institutions":[{"id":"https://openalex.org/I126307644","display_name":"University of Iowa","ror":"https://ror.org/036jqmy94","country_code":"US","type":"education","lineage":["https://openalex.org/I126307644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaogang Du","raw_affiliation_strings":["Electrical and Computer Engineering, University of Iowa, Iowa, IA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Iowa, Iowa, IA, USA","institution_ids":["https://openalex.org/I126307644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077101123","display_name":"S.M. Reddy","orcid":"https://orcid.org/0000-0001-9208-8262"},"institutions":[{"id":"https://openalex.org/I126307644","display_name":"University of Iowa","ror":"https://ror.org/036jqmy94","country_code":"US","type":"education","lineage":["https://openalex.org/I126307644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.M. Reddy","raw_affiliation_strings":["Electrical and Computer Engineering, University of Iowa, Iowa, IA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Iowa, Iowa, IA, USA","institution_ids":["https://openalex.org/I126307644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057262572","display_name":"D.E. Ross","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.E. Ross","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020407423","display_name":"Wu-Tung Cheng","orcid":"https://orcid.org/0000-0001-6327-2394"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wu-Tung Cheng","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015884940","display_name":"J. Rayhawk","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Rayhawk","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":null,"first_page":"243","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7544031143188477},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6055170297622681},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5597897171974182},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5546330213546753},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.539105236530304},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4992969036102295},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.49579891562461853},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4621044099330902},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4545336365699768},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.23715811967849731},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.20728933811187744},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.10615971684455872}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7544031143188477},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6055170297622681},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5597897171974182},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5546330213546753},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.539105236530304},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4992969036102295},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.49579891562461853},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4621044099330902},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4545336365699768},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.23715811967849731},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.20728933811187744},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.10615971684455872},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.2004.1299250","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2004.1299250","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd IEEE VLSI Test Symposium, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W1501552401","https://openalex.org/W1977765666","https://openalex.org/W2105975226","https://openalex.org/W2106935654","https://openalex.org/W2109864646","https://openalex.org/W2115521620","https://openalex.org/W2121708049","https://openalex.org/W2131508353","https://openalex.org/W2143535677","https://openalex.org/W2150714491","https://openalex.org/W2155599474","https://openalex.org/W2168086263","https://openalex.org/W4238535867","https://openalex.org/W4247767635","https://openalex.org/W4254570758"],"related_works":["https://openalex.org/W4285245242","https://openalex.org/W2019238062","https://openalex.org/W3049130895","https://openalex.org/W3008068282","https://openalex.org/W2185658074","https://openalex.org/W2184185181","https://openalex.org/W2557931434","https://openalex.org/W3029446734","https://openalex.org/W2140395285","https://openalex.org/W2132401245"],"abstract_inverted_index":{"A":[0],"memory":[1,38,92,133,152],"BIST":[2,29,99,153],"enhancement,":[3],"ESP":[4,72,84,127,170],"short":[5],"for":[6,41,94,129,174,181],"exercising":[7],"system":[8,49,61,122,141],"paths,":[9,126],"is":[10],"described":[11],"that":[12,39,131,160],"allows":[13,128],"the":[14,34,37,42,60,65,78,91,98,112,118,121,132,140,182,187,190],"efficiency":[15],"and":[16,124,157],"functional":[17,194],"capabilities":[18],"of":[19,36,120,139,189],"standard":[20],"approaches":[21],"while":[22],"addressing":[23],"two":[24],"important":[25],"problems.":[26],"Conventional":[27],"Memory":[28],"techniques":[30],"require":[31],"MUXes":[32,56],"at":[33],"inputs":[35,43],"allow":[40],"to":[44,64,89,97,111,166,193],"be":[45,172,179],"driven":[46],"either":[47],"by":[48,52,76],"signals":[50],"or":[51,163],"test":[53],"signals.":[54],"These":[55],"add":[57],"delays,":[58],"in":[59],"path":[62],"going":[63],"memory,":[66],"which":[67,184],"often":[68],"has":[69],"critical":[70],"timing.":[71],"eliminates":[73],"such":[74],"delays":[75,119],"implementing":[77],"MUXing":[79],"function":[80],"'before'":[81],"scan":[82,87,114],"cells.":[83,115],"also":[85],"uses":[86],"cells":[88],"capture":[90],"output":[93,102,125],"feeding":[95],"back":[96],"controller.":[100],"This":[101],"may":[103,178],"have":[104],"traveled":[105],"through":[106],"some":[107],"logic":[108],"before":[109],"getting":[110],"recording":[113],"By":[116],"including":[117],"input":[123],"verifying":[130],"will":[134],"work":[135],"correctly":[136],"as":[137,145],"part":[138],"rather":[142],"than":[143],"just":[144],"an":[146],"isolated":[147],"unit.":[148],"Using":[149],"ESP,":[150],"a":[151],"can":[154,171],"catch":[155,167],"transition":[156],"delay":[158,192],"faults":[159],"are":[161],"impractical,":[162],"even":[164],"impossible,":[165],"otherwise.":[168],"Therefore,":[169],"useful":[173],"all":[175],"memories":[176,183],"but":[177],"crucial":[180],"cannot":[185],"tolerate":[186],"addition":[188],"MUX":[191],"paths.":[195]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
