{"id":"https://openalex.org/W2109187794","doi":"https://doi.org/10.1109/vtest.2004.1299249","title":"Reducing embedded SRAM test time under redundancy constraints","display_name":"Reducing embedded SRAM test time under redundancy constraints","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2109187794","doi":"https://doi.org/10.1109/vtest.2004.1299249","mag":"2109187794"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.2004.1299249","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2004.1299249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd IEEE VLSI Test Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100612196","display_name":"Baosheng Wang","orcid":"https://orcid.org/0000-0002-2272-9623"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Baosheng Wang","raw_affiliation_strings":["SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081903107","display_name":"Jixiang Yang","orcid":"https://orcid.org/0000-0002-9631-2046"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Yang","raw_affiliation_strings":["SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070976788","display_name":"J. Cicalo","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Cicalo","raw_affiliation_strings":["SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062724257","display_name":"A. Ivanov","orcid":"https://orcid.org/0000-0002-0882-6750"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Ivanov","raw_affiliation_strings":["SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada#TAB#","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108606295","display_name":"Y. Zorian","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Zorian","raw_affiliation_strings":["Virage Logic Corporation, India","[Virage Logic Corporation, India]"],"affiliations":[{"raw_affiliation_string":"Virage Logic Corporation, India","institution_ids":[]},{"raw_affiliation_string":"[Virage Logic Corporation, India]","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100612196"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.0532,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76601853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"237","last_page":"242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7855165600776672},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.782508373260498},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7118297219276428},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4456949234008789},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4221770465373993},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3678189516067505},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3572345972061157},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19452691078186035},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18331092596054077},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07885569334030151}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7855165600776672},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.782508373260498},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7118297219276428},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4456949234008789},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4221770465373993},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3678189516067505},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3572345972061157},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19452691078186035},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18331092596054077},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07885569334030151}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.2004.1299249","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2004.1299249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd IEEE VLSI Test Symposium, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W2062268758","https://openalex.org/W2084429305","https://openalex.org/W2098112833","https://openalex.org/W2106246015","https://openalex.org/W2106935654","https://openalex.org/W2121938580","https://openalex.org/W2124154431","https://openalex.org/W2129780639","https://openalex.org/W2148866533","https://openalex.org/W2150068225","https://openalex.org/W2151824694","https://openalex.org/W2152456874","https://openalex.org/W2156041716","https://openalex.org/W2586375416","https://openalex.org/W4243092325","https://openalex.org/W4256124496","https://openalex.org/W6682542263","https://openalex.org/W6682746215"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W2109451123","https://openalex.org/W4378977321","https://openalex.org/W1976168335","https://openalex.org/W3211992815","https://openalex.org/W2067279514"],"abstract_inverted_index":{"Increasingly":[0],"dense":[1],"SRAMs":[2,91],"of":[3,67,134],"various":[4],"bit":[5],"capacities,":[6],"embedded":[7,76,90],"within":[8],"current":[9],"and":[10,45,60,85,100,121,203,205],"future":[11,210],"systems-on-a-chip":[12],"(SoC)":[13],"designs,":[14],"command":[15],"not":[16],"only":[17],"additional":[18],"complexity":[19],"due":[20],"to":[21,32,108,126,168],"required":[22],"redundancy":[23,86],"schemes,":[24],"but":[25],"also":[26,187],"present":[27],"serious":[28],"challenges":[29],"in":[30,212],"regards":[31],"testing.":[33],"In":[34,50],"particular,":[35],"the":[36,55,65,70,81,111,219],"time":[37,62,160],"needed":[38],"for":[39,74,97,145,172,199,209],"testing":[40,66,98],"data":[41],"retention":[42],"faults":[43],"(DRFs)":[44],"non-DRFs":[46,99],"is":[47,193],"growing":[48],"rapidly.":[49],"this":[51,127,190],"paper,":[52],"we":[53,130],"consider":[54],"overall":[56],"production":[57],"gain":[58],"(OPG)":[59],"delay":[61],"associated":[63],"with":[64,152,176,201],"DRFs":[68],"as":[69,116],"two":[71],"selection":[72],"factors":[73,104],"classifying":[75],"SRAMs,":[77],"where":[78],"OPG":[79],"quantifies":[80],"trade-offs":[82],"between":[83],"yield":[84],"area":[87],"overhead.":[88],"These":[89],"are":[92,106,114],"categorized":[93],"into":[94],"four":[95,112,135],"categories":[96,113],"DRFs.":[101],"Since":[102],"both":[103],"above":[105],"related":[107],"memory":[109],"capacity,":[110],"named":[115],"very":[117,122],"small,":[118,119],"large,":[120],"large":[123],"types.":[124],"According":[125],"simple":[128],"classification,":[129],"generate":[131],"a":[132,150],"set":[133],"March":[136,142,153,223],"test":[137,159],"algorithms":[138,221],"from":[139],"an":[140],"existing":[141],"SRD":[143,224],"algorithm":[144],"each":[146],"category":[147],"respectively.":[148],"As":[149],"comparison":[151,220],"SRD,":[154],"our":[155],"investigations":[156],"reveal":[157],"that":[158,189],"can":[161],"generally":[162],"be":[163],"at":[164],"least":[165],"halved":[166],"down":[167],"22":[169],"nm":[170],"technology":[171],"all":[173],"capacity":[174,207],"e-SRAMs":[175,211],"different":[177],"IO":[178],"numbers":[179],"without":[180],"losing":[181],"defect":[182],"coverage.":[183],"The":[184],"evaluation":[185],"results":[186],"show":[188],"reduction":[191],"ratio":[192],"always":[194],"no":[195,215],"less":[196],"than":[197],"50%":[198],"those":[200],"larger":[202,204,206],"predicted":[208],"ITRS":[213],"documents":[214],"matter":[216],"what":[217],"complex":[218],"besides":[222],"are.":[225]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}