{"id":"https://openalex.org/W1819724419","doi":"https://doi.org/10.1109/vtest.2003.1197683","title":"Design for self-checking and self-timed datapath","display_name":"Design for self-checking and self-timed datapath","publication_year":2003,"publication_date":"2003-10-31","ids":{"openalex":"https://openalex.org/W1819724419","doi":"https://doi.org/10.1109/vtest.2003.1197683","mag":"1819724419"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.2003.1197683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2003.1197683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 21st VLSI Test Symposium, 2003.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113438061","display_name":"Jing-ling Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Jing-ling Yang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong, China","Dept. of Electr. & Electron. Eng., Hong Kong Univ., , China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I889458895"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Hong Kong Univ., , China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020902784","display_name":"Chiu\u2010Sing Choy","orcid":"https://orcid.org/0000-0002-8370-3144"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chiu-sing Choy","raw_affiliation_strings":["Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103563899","display_name":"Cheong-Fat Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cheong-fat Chan","raw_affiliation_strings":["Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011118103","display_name":"Kong-pong Pun","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kong-pong Pun","raw_affiliation_strings":["Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5113438061"],"corresponding_institution_ids":["https://openalex.org/I889458895"],"apc_list":null,"apc_paid":null,"fwci":1.0432,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76010943,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"417","last_page":"422"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9868043661117554},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.772263765335083},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6656835079193115},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46411851048469543},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46254488825798035},{"id":"https://openalex.org/keywords/cascode","display_name":"Cascode","score":0.4289371073246002},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42825910449028015},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4230811297893524},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4117783010005951},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3339568078517914},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.30908626317977905},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.282725989818573},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.18312737345695496},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15384018421173096},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07335332036018372}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9868043661117554},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.772263765335083},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6656835079193115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46411851048469543},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46254488825798035},{"id":"https://openalex.org/C2775946640","wikidata":"https://www.wikidata.org/wiki/Q1735017","display_name":"Cascode","level":4,"score":0.4289371073246002},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42825910449028015},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4230811297893524},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4117783010005951},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3339568078517914},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30908626317977905},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.282725989818573},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18312737345695496},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15384018421173096},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07335332036018372},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.0},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.2003.1197683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2003.1197683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 21st VLSI Test Symposium, 2003.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1483902580","https://openalex.org/W1489870749","https://openalex.org/W1601585824","https://openalex.org/W1821179458","https://openalex.org/W1839367760","https://openalex.org/W2031234016","https://openalex.org/W2035720669","https://openalex.org/W2059456074","https://openalex.org/W2068355008","https://openalex.org/W2079389379","https://openalex.org/W2102785640","https://openalex.org/W2102969748","https://openalex.org/W2141718959","https://openalex.org/W2168281491","https://openalex.org/W6629399013","https://openalex.org/W6638410685"],"related_works":["https://openalex.org/W2166021916","https://openalex.org/W1903431847","https://openalex.org/W1994884893","https://openalex.org/W1839177134","https://openalex.org/W3149874529","https://openalex.org/W2135482679","https://openalex.org/W2084005807","https://openalex.org/W2137686989","https://openalex.org/W2004001588","https://openalex.org/W2375695813"],"abstract_inverted_index":{"This":[0],"work":[1],"examines":[2],"the":[3,43],"inherent":[4],"self-checking":[5,25],"property":[6],"of":[7,55],"a":[8,22,61],"latch-free":[9],"dynamic":[10,27],"asynchronous":[11,28],"datapath":[12,29,44],"(LFDAD)":[13],"using":[14],"differential":[15],"cascode":[16],"voltage":[17],"switch":[18],"logic":[19],"(DCVSL).":[20],"Consequently,":[21],"highly":[23],"efficient":[24,52],"(SC)":[26],"architecture":[30],"is":[31,51],"presented.":[32],"In":[33],"this":[34],"architecture,":[35],"no":[36],"hardware":[37],"needs":[38],"to":[39,42,45,64],"be":[40],"added":[41],"achieve":[46],"self-checking.":[47],"The":[48],"presented":[49],"implementation":[50],"in":[53],"terms":[54],"speed":[56],"and":[57,59],"area":[58],"represents":[60],"new":[62],"approach":[63],"fault-tolerant":[65],"design.":[66]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
