{"id":"https://openalex.org/W2153301553","doi":"https://doi.org/10.1109/vtest.2003.1197667","title":"Design and optimization of multi-level TAM architectures for hierarchical SOCs","display_name":"Design and optimization of multi-level TAM architectures for hierarchical SOCs","publication_year":2003,"publication_date":"2003-10-31","ids":{"openalex":"https://openalex.org/W2153301553","doi":"https://doi.org/10.1109/vtest.2003.1197667","mag":"2153301553"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.2003.1197667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2003.1197667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 21st VLSI Test Symposium, 2003.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019420188","display_name":"V. Iyengar","orcid":"https://orcid.org/0000-0001-6696-3940"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V. Iyengar","raw_affiliation_strings":["IBM Microelectronics, Essex Junction, VT, USA"],"affiliations":[{"raw_affiliation_string":"IBM Microelectronics, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033880864","display_name":"Krishnendu Chakrabarty","orcid":"https://orcid.org/0000-0003-4475-6435"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Chakrabarty","raw_affiliation_strings":["Electrical & Computer Engineering, Duke University, Durham, NC, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060097429","display_name":"Mark D. Krasniewski","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.D. Krasniewski","raw_affiliation_strings":["Electrical & Computer Engineering, Duke University, Durham, NC, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038596134","display_name":"G. Naveen Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G.N. Kumar","raw_affiliation_strings":["Electrical & Computer Engineering, Duke University, Durham, NC, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5019420188"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":2.767,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.9079396,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"299","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9851999878883362,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6842256784439087},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6834349632263184},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.5803511142730713},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5648271441459656},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.5325264930725098},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5261237621307373},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5160055160522461},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.476754754781723}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6842256784439087},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6834349632263184},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.5803511142730713},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5648271441459656},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.5325264930725098},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5261237621307373},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5160055160522461},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.476754754781723},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vtest.2003.1197667","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2003.1197667","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 21st VLSI Test Symposium, 2003.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.7.7763","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.7763","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.duke.edu/~krish/VTS_03_Iyengar.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1501987125","https://openalex.org/W1528872186","https://openalex.org/W1536055443","https://openalex.org/W1570296235","https://openalex.org/W1596724070","https://openalex.org/W2104548962","https://openalex.org/W2110129459","https://openalex.org/W2124658657","https://openalex.org/W2133238467","https://openalex.org/W2149608454","https://openalex.org/W2151243068","https://openalex.org/W2165642910","https://openalex.org/W2166680980","https://openalex.org/W2169449309","https://openalex.org/W2170533364","https://openalex.org/W4230515438","https://openalex.org/W4252472882","https://openalex.org/W4255588132","https://openalex.org/W7029018936"],"related_works":["https://openalex.org/W17155033","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W4312814274","https://openalex.org/W1590307681","https://openalex.org/W2536018345","https://openalex.org/W4285370786","https://openalex.org/W2296488620","https://openalex.org/W2358353312","https://openalex.org/W2353836703"],"abstract_inverted_index":{"Multi-level":[0],"TAM":[1,22,30],"optimization":[2,23],"is":[3],"necessary":[4],"for":[5,32,67],"modular":[6],"testing":[7],"of":[8],"hierarchical":[9,21],"SOCs":[10,14],"that":[11,25,39],"contain":[12],"older-generation":[13],"as":[15],"embedded":[16],"cores.":[17],"We":[18],"present":[19],"two":[20],"flows":[24],"exploit":[26],"recent":[27],"advances":[28],"in":[29],"design":[31,52],"flattened":[33],"SOC":[34,61,70],"hierarchies.":[35],"Unlike":[36],"prior":[37],"methods":[38,46],"assume":[40],"flat":[41],"test":[42,71],"hierarchies,":[43],"the":[44,56,60],"proposed":[45],"are":[47,65],"directly":[48],"applicable":[49],"to":[50],"real-world":[51],"transfer":[53],"models":[54],"between":[55],"core":[57],"vendor":[58],"and":[59],"integrator.":[62],"Experimental":[63],"results":[64],"presented":[66],"four":[68],"ITC'02":[69],"benchmarks.":[72]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
