{"id":"https://openalex.org/W4401880080","doi":"https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631399","title":"A Monolithic 5.7A/mm<sup>2</sup> 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs","display_name":"A Monolithic 5.7A/mm<sup>2</sup> 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs","publication_year":2024,"publication_date":"2024-06-16","ids":{"openalex":"https://openalex.org/W4401880080","doi":"https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631399"},"language":"en","primary_location":{"id":"doi:10.1109/vlsitechnologyandcir46783.2024.10631399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Y. Jingshu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Y. Jingshu","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052857735","display_name":"Xiaosen Liu","orcid":"https://orcid.org/0000-0003-2767-215X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaosen Liu","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023396373","display_name":"Minxiang Gong","orcid":"https://orcid.org/0000-0002-5426-7697"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Minxiang Gong","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063453028","display_name":"Nicolas Butzen","orcid":"https://orcid.org/0000-0002-4242-5563"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nicolas Butzen","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054252150","display_name":"Sheldon Weng","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheldon Weng","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043243464","display_name":"Harish K. Krishnamurthy","orcid":"https://orcid.org/0000-0001-5927-8339"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harish K Krishnamurthy","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061932619","display_name":"Krishnan Ravichandran","orcid":"https://orcid.org/0000-0003-2271-4314"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnan Ravichandran","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045804811","display_name":"Ramez Hosseinian Ahangharnejhad","orcid":"https://orcid.org/0000-0003-1398-0397"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramez H Ahangharnejhad","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106737433","display_name":"Waldemer Jim","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Waldemer Jim","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111301666","display_name":"Pelto Christopher","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pelto Christopher","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067753561","display_name":"James Tschanz","orcid":"https://orcid.org/0000-0003-0317-4332"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James W Tschanz","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Intel Labs,Hillsboro,Oregon,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs,Hillsboro,Oregon,USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":12,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.8429,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.73203399,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.9842000007629395,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7494696974754333},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7340397834777832},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.661293625831604},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.5922921895980835},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5818948745727539},{"id":"https://openalex.org/keywords/regulator","display_name":"Regulator","score":0.5562399625778198},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5468137860298157},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.4909997284412384},{"id":"https://openalex.org/keywords/low-dropout-regulator","display_name":"Low-dropout regulator","score":0.4686780571937561},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4384724199771881},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.40096625685691833},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.38276243209838867},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.38167816400527954},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3742721676826477},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.3552105128765106},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27593994140625},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.1675063967704773},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10265618562698364}],"concepts":[{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7494696974754333},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7340397834777832},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.661293625831604},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.5922921895980835},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5818948745727539},{"id":"https://openalex.org/C6929976","wikidata":"https://www.wikidata.org/wiki/Q3771881","display_name":"Regulator","level":3,"score":0.5562399625778198},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5468137860298157},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.4909997284412384},{"id":"https://openalex.org/C140501009","wikidata":"https://www.wikidata.org/wiki/Q6692746","display_name":"Low-dropout regulator","level":5,"score":0.4686780571937561},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4384724199771881},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40096625685691833},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.38276243209838867},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.38167816400527954},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3742721676826477},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.3552105128765106},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27593994140625},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.1675063967704773},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10265618562698364},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsitechnologyandcir46783.2024.10631399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8100000023841858,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W4252026737"],"related_works":["https://openalex.org/W1982997428","https://openalex.org/W2044172536","https://openalex.org/W2371498377","https://openalex.org/W2991752277","https://openalex.org/W2476208285","https://openalex.org/W2371267182","https://openalex.org/W2083807160","https://openalex.org/W2736802678","https://openalex.org/W2380852726","https://openalex.org/W2549277932"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,49],"monolithic":[4,62],"Multi-stage":[5],"Modular":[6],"Switched":[7],"Capacitor":[8],"Voltage":[9],"Regulator":[10],"(MMSCVR)":[11],"in":[12,31],"16nm":[13],"CMOS":[14],"with":[15,48,73],"scalable":[16],"design":[17],"(up":[18],"to":[19],"7A),":[20],"self-timed":[21],"deadtime":[22],"generator,":[23],"and":[24,41],"safe":[25],"startup":[26],"for":[27],"vertical":[28],"power":[29],"delivery":[30],"heterogeneous":[32],"3D-ICs.":[33],"The":[34],"proposed":[35],"MMSCVR":[36],"demonstrates":[37],"90.6%":[38],"peak":[39,45],"efficiency":[40],"5.7A/mm<sup":[42],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[43],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[44],"current":[46,68],"density":[47,69],"3V-to-1V":[50],"conversion":[51],"\u2212":[52],"4.9\u00d7":[53],"higher":[54,67],"than":[55,70],"state-of-the-art.":[56],"It":[57],"is":[58],"also":[59],"the":[60],"first":[61],"4V-to-1V":[63],"MMSCVR,":[64],"achieving":[65],"7.8\u00d7":[66],"prior":[71],"arts":[72],"off-chip":[74],"capacitors.":[75]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3}],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}