{"id":"https://openalex.org/W4286571893","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830470","title":"A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS","display_name":"A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS","publication_year":2022,"publication_date":"2022-06-12","ids":{"openalex":"https://openalex.org/W4286571893","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830470"},"language":"en","primary_location":{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830470","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074467331","display_name":"Raghavan Kumar","orcid":"https://orcid.org/0000-0001-7399-1886"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Raghavan Kumar","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078003656","display_name":"Vikram Suresh","orcid":"https://orcid.org/0000-0001-8879-1967"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vikram Suresh","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003357019","display_name":"Sachin Taneja","orcid":"https://orcid.org/0000-0002-4590-7875"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin Taneja","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Anders","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven Hsu","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu Mathew","raw_affiliation_strings":["Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5074467331"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2078,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.39522732,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"138","last_page":"139"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/side-channel-attack","display_name":"Side channel attack","score":0.7078297138214111},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6252915263175964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6004492044448853},{"id":"https://openalex.org/keywords/advanced-encryption-standard","display_name":"Advanced Encryption Standard","score":0.5180680751800537},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.4670476019382477},{"id":"https://openalex.org/keywords/aes-implementations","display_name":"AES implementations","score":0.4609532654285431},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4413757622241974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40154868364334106},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3397749662399292},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3369913101196289},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.3164627254009247},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2830798625946045},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21117272973060608},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16594365239143372},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1482754945755005}],"concepts":[{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.7078297138214111},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6252915263175964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6004492044448853},{"id":"https://openalex.org/C94520183","wikidata":"https://www.wikidata.org/wiki/Q190746","display_name":"Advanced Encryption Standard","level":3,"score":0.5180680751800537},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.4670476019382477},{"id":"https://openalex.org/C46331935","wikidata":"https://www.wikidata.org/wiki/Q4651362","display_name":"AES implementations","level":4,"score":0.4609532654285431},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4413757622241974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40154868364334106},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3397749662399292},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3369913101196289},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.3164627254009247},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2830798625946045},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21117272973060608},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16594365239143372},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1482754945755005}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830470","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6499999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2161048573","https://openalex.org/W1703859826","https://openalex.org/W2392288291","https://openalex.org/W3121248233","https://openalex.org/W2393941228","https://openalex.org/W4248712873","https://openalex.org/W2541639725","https://openalex.org/W3208859339","https://openalex.org/W4255075415","https://openalex.org/W4253685677"],"abstract_inverted_index":{"A":[0],"side-channel-attack":[1,38],"(SCA)":[2],"resistant":[3],"AES":[4],"engine":[5],"with":[6,40],"multiplicative-masked":[7],"Sboxes":[8],"is":[9],"fabricated":[10],"in":[11,37],"Intel":[12],"4":[13],"CMOS,":[14],"achieving":[15],"1.8\u00d7":[16],"lower":[17],"area":[18],"overhead":[19],"compared":[20],"to":[21],"conventional":[22],"additive-masked":[23],"implementations.":[24],"Balanced":[25],"dual-rail":[26],"detector":[27],"circuits":[28],"pre-empt":[29],"zero-value":[30],"attacks":[31],"while":[32],"providing":[33],"a":[34,41],"34,000\u00d7":[35],"increase":[36],"resistance,":[39],"measured":[42],"minimum-traces-to-disclose":[43],"(MTD)":[44],"of":[45],"850M":[46],"encryption":[47],"traces.":[48]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
