{"id":"https://openalex.org/W4286571722","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322","title":"A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference","display_name":"A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference","publication_year":2022,"publication_date":"2022-06-12","ids":{"openalex":"https://openalex.org/W4286571722","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322"},"language":"en","primary_location":{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074357549","display_name":"Hechen Wang","orcid":"https://orcid.org/0000-0001-8437-7726"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hechen Wang","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102842702","display_name":"Renzhi Liu","orcid":"https://orcid.org/0000-0002-4462-8006"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Renzhi Liu","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070757248","display_name":"Richard Dorrance","orcid":"https://orcid.org/0000-0003-4756-5394"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard Dorrance","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072562864","display_name":"Deepak Dasalukunte","orcid":"https://orcid.org/0000-0002-5973-0193"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deepak Dasalukunte","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052857735","display_name":"Xiaosen Liu","orcid":"https://orcid.org/0000-0003-2767-215X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaosen Liu","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028630331","display_name":"Dan Lake","orcid":"https://orcid.org/0000-0002-2590-1900"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Lake","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059381050","display_name":"Brent Carlton","orcid":"https://orcid.org/0000-0003-4542-4715"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brent Carlton","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108553782","display_name":"May Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"May Wu","raw_affiliation_strings":["Intel Corporation,Intel Labs,Hillsboro,OR,USA","Intel Labs, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Intel Labs,Hillsboro,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5074357549"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":12.8969,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.9956442,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"36","last_page":"37"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7682620286941528},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6024373769760132},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5974957346916199},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5378668904304504},{"id":"https://openalex.org/keywords/tops","display_name":"TOPS","score":0.5377405285835266},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4831763803958893},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.47961175441741943},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4532516896724701},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.45273536443710327},{"id":"https://openalex.org/keywords/charge","display_name":"Charge (physics)","score":0.4239906072616577},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4215274155139923},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.402060329914093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.37839987874031067},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3602164685726166},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3481578230857849},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34698739647865295},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3058965802192688},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28037405014038086},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2779642641544342},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19282463192939758},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16545560956001282},{"id":"https://openalex.org/keywords/quantum-mechanics","display_name":"Quantum mechanics","score":0.08842095732688904}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7682620286941528},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6024373769760132},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5974957346916199},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5378668904304504},{"id":"https://openalex.org/C2777675136","wikidata":"https://www.wikidata.org/wiki/Q835642","display_name":"TOPS","level":3,"score":0.5377405285835266},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4831763803958893},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.47961175441741943},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4532516896724701},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.45273536443710327},{"id":"https://openalex.org/C188082385","wikidata":"https://www.wikidata.org/wiki/Q73792","display_name":"Charge (physics)","level":2,"score":0.4239906072616577},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4215274155139923},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.402060329914093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.37839987874031067},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3602164685726166},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3481578230857849},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34698739647865295},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3058965802192688},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28037405014038086},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2779642641544342},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19282463192939758},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16545560956001282},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.08842095732688904},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C159737794","wikidata":"https://www.wikidata.org/wiki/Q124274","display_name":"Azimuth","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2811109569","https://openalex.org/W2385933648","https://openalex.org/W2381557761","https://openalex.org/W2067978743","https://openalex.org/W1996292569","https://openalex.org/W2113085768","https://openalex.org/W2299607813","https://openalex.org/W2514866747","https://openalex.org/W2393218002","https://openalex.org/W4245369157"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"SRAM-based":[4],"analog":[5,65],"Compute-in-Memory":[6],"(CiM)":[7],"macro":[8],"in":[9,33,56],"22":[10],"nm":[11],"CMOS":[12],"process.":[13],"By":[14],"introducing":[15],"a":[16],"C-2C":[17],"capacitor":[18],"ladder-based":[19],"charge":[20],"domain":[21],"computing":[22],"scheme,":[23],"the":[24,71],"CiM":[25],"prototype":[26],"chip":[27],"demonstrates":[28],"2k":[29],"multiply-accumulation":[30],"(MAC)":[31],"operations":[32],"one":[34],"clock":[35],"cycle":[36],"and":[37,44,60],"achieves":[38],"32.2":[39],"TOPS/W":[40],"peak":[41,50],"energy":[42],"efficiency":[43,52],"4.0":[45],"TOPS/mm":[46],"<sup":[47],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[48],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[49],"area":[51],"with":[53],"8-bit":[54],"precision":[55],"both":[57],"input":[58],"activation":[59],"weight.":[61],"A":[62],"variety":[63],"of":[64],"impairment":[66],"factors":[67],"were":[68],"analyzed":[69],"during":[70],"testchip":[72],"implementation":[73],"to":[74],"ensure":[75],"sufficiently":[76],"high":[77],"multibit":[78],"linearity.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":16},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":2}],"updated_date":"2026-02-18T06:20:13.636215","created_date":"2025-10-10T00:00:00"}
