{"id":"https://openalex.org/W2004449536","doi":"https://doi.org/10.1109/vlsisoc.2011.6081665","title":"Combinational logic synthesis for material implication","display_name":"Combinational logic synthesis for material implication","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2004449536","doi":"https://doi.org/10.1109/vlsisoc.2011.6081665","mag":"2004449536"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2011.6081665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["MPSoC Architectures, UMIC, RWTH Aachen University, Germany","MPSoC Architectures, UMIC, RWTH Aachen University, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"MPSoC Architectures, UMIC, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"MPSoC Architectures, UMIC, RWTH Aachen University, Germany#TAB#","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057154947","display_name":"Z. Rakosi","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Zoltan Rakosi","raw_affiliation_strings":["MPSoC Architectures, UMIC, RWTH Aachen University, Germany","MPSoC Architectures, UMIC, RWTH Aachen University, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"MPSoC Architectures, UMIC, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"MPSoC Architectures, UMIC, RWTH Aachen University, Germany#TAB#","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089860351"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.2699,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.60150645,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"200","last_page":"203"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12236","display_name":"Photoreceptor and optogenetics research","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6963428258895874},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.6735289096832275},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6559246778488159},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.6417933702468872},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5417587757110596},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.49026110768318176},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4864613711833954},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4620354473590851},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.42679911851882935},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.42064887285232544},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35103100538253784},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34761324524879456},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34380608797073364},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3348296582698822},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21142587065696716},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17862585186958313},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1153717041015625}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6963428258895874},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.6735289096832275},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6559246778488159},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.6417933702468872},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5417587757110596},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.49026110768318176},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4864613711833954},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4620354473590851},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.42679911851882935},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.42064887285232544},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35103100538253784},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34761324524879456},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34380608797073364},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3348296582698822},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21142587065696716},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17862585186958313},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1153717041015625},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsisoc.2011.6081665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:128240","is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/record/128240","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC 2011) : Kowloon, Hong Kong, 3 - 5 October 2011<br/>2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Hong Kong, Hong Kong, 2011-10-03 - 2011-10-05","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W31150501","https://openalex.org/W1548459443","https://openalex.org/W1980078498","https://openalex.org/W2013055927","https://openalex.org/W2025674646","https://openalex.org/W2064756415","https://openalex.org/W2100465945","https://openalex.org/W2108340689","https://openalex.org/W2112181056","https://openalex.org/W2113105904","https://openalex.org/W2122148191","https://openalex.org/W2136288682","https://openalex.org/W2165643425","https://openalex.org/W6601244955"],"related_works":["https://openalex.org/W1939541994","https://openalex.org/W1966764473","https://openalex.org/W818963952","https://openalex.org/W2018106661","https://openalex.org/W2169337913","https://openalex.org/W2072840391","https://openalex.org/W2039140951","https://openalex.org/W2107594749","https://openalex.org/W2157277696","https://openalex.org/W4242010157"],"abstract_inverted_index":{"The":[0,80],"smooth":[1],"scaling":[2],"of":[3,47,82,114],"technology":[4],"over":[5],"past":[6],"decades":[7],"is":[8,37,53,68],"returning":[9],"diminished":[10],"profits":[11],"as":[12,90,92,123],"researchers":[13],"are":[14,130,135],"trying":[15],"to":[16,72,86,93,137],"cope":[17],"with":[18],"several":[19],"challenges":[20],"posed":[21],"by":[22],"CMOS":[23],"devices.":[24],"As":[25],"a":[26,44,64,76,83,99,115],"result,":[27],"quest":[28],"for":[29,33,102],"novel":[30],"physical":[31],"media":[32],"storage":[34],"and":[35,132],"computing":[36],"currently":[38],"an":[39],"important":[40],"research":[41],"pursuit.":[42],"Recently":[43],"new":[45,133],"kind":[46],"passive":[48],"electrical":[49],"device":[50,85],"called":[51],"memristor":[52],"proposed,":[54],"which":[55],"can":[56],"retain":[57,94],"its":[58,95],"state":[59,96],"via":[60],"the":[61,110,124,139],"resistance":[62],"in":[63],"non-volatile":[65],"fashion.":[66],"It":[67],"also":[69],"experimentally":[70],"demonstrated":[71],"perform":[73],"material":[74],"implication,":[75],"fundamental":[77],"logical":[78,88],"operation.":[79],"capability":[81],"memristive":[84,121],"do":[87],"operations":[89],"well":[91],"makes":[97],"it":[98],"promising":[100],"candidate":[101],"future":[103],"technologies.":[104],"In":[105],"this":[106],"paper,":[107],"we":[108],"investigate":[109],"approximate":[111],"implementation":[112],"cost":[113],"multi-level":[116],"combinational":[117],"logic":[118],"while":[119],"using":[120],"switches":[122],"target":[125],"technology.":[126],"Traditional":[127],"synthesis":[128],"algorithms":[129],"extended":[131],"heuristics":[134],"suggested":[136],"reduce":[138],"costs":[140],"significantly.":[141]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
