{"id":"https://openalex.org/W2009477135","doi":"https://doi.org/10.1109/vlsisoc.2011.6081651","title":"Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts","display_name":"Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2009477135","doi":"https://doi.org/10.1109/vlsisoc.2011.6081651","mag":"2009477135"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2011.6081651","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007908609","display_name":"Oliver Mitea","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Oliver Mitea","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","institution_ids":["https://openalex.org/I114090438"]},{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017152441","display_name":"Markus Mei\u00dfner","orcid":"https://orcid.org/0000-0002-5630-587X"},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Meissner","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","institution_ids":["https://openalex.org/I114090438"]},{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038049766","display_name":"Lars Hedrich","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lars Hedrich","raw_affiliation_strings":["Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt, Main, Germany","institution_ids":["https://openalex.org/I114090438"]},{"raw_affiliation_string":"Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8109,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.75361903,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"78","last_page":"81"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.718890905380249},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6309154629707336},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6211695671081543},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5854754447937012},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.560838520526886},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.534159779548645},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5283147692680359},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5052333474159241},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4840892553329468},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.4568016231060028},{"id":"https://openalex.org/keywords/network-synthesis-filters","display_name":"Network synthesis filters","score":0.41998013854026794},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.38823065161705017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3750186562538147},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19501152634620667},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19182485342025757},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11809048056602478}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.718890905380249},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6309154629707336},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6211695671081543},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5854754447937012},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.560838520526886},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.534159779548645},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5283147692680359},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5052333474159241},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4840892553329468},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.4568016231060028},{"id":"https://openalex.org/C51297928","wikidata":"https://www.wikidata.org/wiki/Q7001207","display_name":"Network synthesis filters","level":2,"score":0.41998013854026794},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.38823065161705017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3750186562538147},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19501152634620667},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19182485342025757},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11809048056602478},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsisoc.2011.6081651","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W147475332","https://openalex.org/W1540091368","https://openalex.org/W1565462788","https://openalex.org/W2015105542","https://openalex.org/W2116235542","https://openalex.org/W2136486144","https://openalex.org/W2137033438","https://openalex.org/W2147120117","https://openalex.org/W2151778337","https://openalex.org/W2153797910","https://openalex.org/W2169944292","https://openalex.org/W4236195134","https://openalex.org/W6605959832","https://openalex.org/W6682119758"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2375311683","https://openalex.org/W2096437374","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W1943174035","https://openalex.org/W2352072014"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,16,30,35,42,99],"tool":[4],"for":[5,122],"automatic":[6],"analog":[7],"topology":[8],"generation":[9],"and":[10],"subsequent":[11],"sizing.":[12],"For":[13],"this":[14],"purpose":[15],"multistage":[17],"design":[18],"flow":[19],"has":[20,95,102],"been":[21,96,103],"developed.":[22],"To":[23],"synthesize":[24],"new":[25],"circuit":[26],"topologies":[27],"according":[28],"to":[29,87,105],"set":[31,49],"of":[32,44,50,57,113],"given":[33],"specifications,":[34],"hierarchical":[36],"algorithm":[37],"composes":[38],"the":[39,58,61,91,106,123],"circuits":[40,66,117],"using":[41],"library":[43],"basic":[45],"building":[46],"blocks.":[47,59],"A":[48],"constraints":[51],"ensures":[52],"an":[53,110],"electrically":[54],"reasonable":[55],"interconnection":[56],"In":[60],"next":[62],"step":[63],"all":[64],"generated":[65],"are":[67,84,128],"preselected":[68],"by":[69],"symbolic":[70,92],"analysis":[71,93],"methods.":[72],"The":[73],"following":[74],"sizing":[75,107],"is":[76,118],"executed":[77],"with":[78],"SPICE":[79],"accuracy.":[80],"Three":[81],"main":[82],"extensions":[83],"applied,":[85],"compared":[86],"previous":[88],"approaches.":[89],"First,":[90],"methodology":[94],"improved.":[97],"Second,":[98],"yield":[100],"optimization":[101],"included":[104],"step.":[108],"Third,":[109],"automated":[111],"evaluation":[112],"hundreds":[114],"successfully":[115],"sized":[116],"realized":[119],"through":[120,130],"searching":[121],"pareto":[124],"optimal":[125],"designs.":[126],"Results":[127],"shown":[129],"two":[131],"different":[132],"synthesis":[133],"runs,":[134],"generating":[135],"operational":[136],"amplifier":[137],"topologies.":[138]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
