{"id":"https://openalex.org/W2067795940","doi":"https://doi.org/10.1109/vlsisoc.2011.6081605","title":"3-D integration and the limits of silicon computation","display_name":"3-D integration and the limits of silicon computation","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2067795940","doi":"https://doi.org/10.1109/vlsisoc.2011.6081605","mag":"2067795940"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2011.6081605","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081605","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018789044","display_name":"Dinesh Pamunuwa","orcid":"https://orcid.org/0000-0002-4838-7932"},"institutions":[{"id":"https://openalex.org/I67415387","display_name":"Lancaster University","ror":"https://ror.org/04f2nsd36","country_code":"GB","type":"education","lineage":["https://openalex.org/I67415387"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Dinesh Pamunuwa","raw_affiliation_strings":["Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","institution_ids":["https://openalex.org/I67415387"]},{"raw_affiliation_string":"Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom","institution_ids":["https://openalex.org/I67415387"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057329555","display_name":"Matthew Grange","orcid":"https://orcid.org/0009-0007-6898-0454"},"institutions":[{"id":"https://openalex.org/I67415387","display_name":"Lancaster University","ror":"https://ror.org/04f2nsd36","country_code":"GB","type":"education","lineage":["https://openalex.org/I67415387"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Matthew Grange","raw_affiliation_strings":["Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","institution_ids":["https://openalex.org/I67415387"]},{"raw_affiliation_string":"Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom","institution_ids":["https://openalex.org/I67415387"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090054314","display_name":"Roshan Weerasekera","orcid":"https://orcid.org/0000-0002-6287-2731"},"institutions":[{"id":"https://openalex.org/I67415387","display_name":"Lancaster University","ror":"https://ror.org/04f2nsd36","country_code":"GB","type":"education","lineage":["https://openalex.org/I67415387"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Roshan Weerasekera","raw_affiliation_strings":["Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Centre of Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK","institution_ids":["https://openalex.org/I67415387"]},{"raw_affiliation_string":"Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, LA1 4YR, United Kingdom","institution_ids":["https://openalex.org/I67415387"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032163732","display_name":"Axel Jantsch","orcid":"https://orcid.org/0000-0003-2251-0004"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Axel Jantsch","raw_affiliation_strings":["Department of Electronic, Communication, and Software Systems, Royal Institute of Technology (KTH), Kista, Sweden","Dept. of Electronic, Communication, and Software Systems, Royal Institute of Technology (KTH), Forum 120, SE-164 40 Kista, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electronic, Communication, and Software Systems, Royal Institute of Technology (KTH), Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Dept. of Electronic, Communication, and Software Systems, Royal Institute of Technology (KTH), Forum 120, SE-164 40 Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5018789044"],"corresponding_institution_ids":["https://openalex.org/I67415387"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15447993,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":null,"first_page":"343","last_page":"348"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.8137719631195068},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.6312058568000793},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5982661247253418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5873690843582153},{"id":"https://openalex.org/keywords/envelope","display_name":"Envelope (radar)","score":0.5054047107696533},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4916234612464905},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.47784969210624695},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4643939137458801},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.4492737054824829},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.43138325214385986},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.41918444633483887},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4161372780799866},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.39979037642478943},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36349374055862427},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28193047642707825},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2416667342185974},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.21254265308380127},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17865285277366638},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.15899068117141724},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15776842832565308},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14633533358573914},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12924668192863464},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11342212557792664}],"concepts":[{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.8137719631195068},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.6312058568000793},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5982661247253418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5873690843582153},{"id":"https://openalex.org/C65155139","wikidata":"https://www.wikidata.org/wiki/Q5380912","display_name":"Envelope (radar)","level":3,"score":0.5054047107696533},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4916234612464905},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.47784969210624695},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4643939137458801},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.4492737054824829},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43138325214385986},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.41918444633483887},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4161372780799866},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.39979037642478943},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36349374055862427},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28193047642707825},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2416667342185974},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.21254265308380127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17865285277366638},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.15899068117141724},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15776842832565308},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14633533358573914},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12924668192863464},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11342212557792664},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/vlsisoc.2011.6081605","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2011.6081605","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.222.1581","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.222.1581","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.imit.kth.se/%7Eaxel/papers/2011/VLSI_SoC-Dinesh.pdf","raw_type":"text"},{"id":"pmh:oai:research-information.bris.ac.uk:openaire_cris_publications/41d140c3-39ff-4983-a947-1d7d8fcc0103","is_oa":false,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/41d140c3-39ff-4983-a947-1d7d8fcc0103","pdf_url":null,"source":{"id":"https://openalex.org/S7407055359","display_name":"Explore Bristol Research","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Pamunuwa, D, Grange, M, Weerasekera, R & Jantsch, A 2011, 3-D Integration and the Limits of Silicon Computation. in Proc. IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC). pp. 343-348. https://doi.org/10.1109/VLSISoC.2011.6081605","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1599079101","https://openalex.org/W1998202312","https://openalex.org/W2017503457","https://openalex.org/W2037915256","https://openalex.org/W2084416612","https://openalex.org/W2098463182","https://openalex.org/W2100471067","https://openalex.org/W2108880814","https://openalex.org/W2131413854","https://openalex.org/W2133937833","https://openalex.org/W2153215457","https://openalex.org/W2155503253","https://openalex.org/W2159747318","https://openalex.org/W2165021839","https://openalex.org/W2171825402","https://openalex.org/W2253935813","https://openalex.org/W2532645630","https://openalex.org/W2543638529","https://openalex.org/W3139689176","https://openalex.org/W3143002681","https://openalex.org/W4243164749","https://openalex.org/W6654834059"],"related_works":["https://openalex.org/W2027159884","https://openalex.org/W1990828594","https://openalex.org/W2748443500","https://openalex.org/W2089377260","https://openalex.org/W2046139226","https://openalex.org/W2513353273","https://openalex.org/W2549021975","https://openalex.org/W2333804548","https://openalex.org/W4399621287","https://openalex.org/W1968957853"],"abstract_inverted_index":{"The":[0,23],"intrinsic":[1],"computational":[2,25,31],"efficiency":[3,26],"(ICE)":[4],"of":[5,11,14,34,52,80,102],"silicon":[6,86],"defines":[7],"the":[8,12,29,63,77,94,100],"upper":[9,48],"limit":[10],"amount":[13],"computation":[15,51],"within":[16],"a":[17,45,53],"given":[18,54],"technology":[19,83,123],"and":[20,28,40,74,76,96,110,116,121],"power":[21],"envelope.":[22],"effective":[24,30],"(ECE)":[27],"density":[32],"(ECD)":[33],"silicon,":[35],"by":[36,71],"taking":[37],"computation,":[38,72],"memory":[39,64,73,106],"communication":[41],"into":[42],"account,":[43],"offer":[44],"more":[46],"realistic":[47],"bound":[49],"for":[50,113],"technology.":[55],"Among":[56],"other":[57],"factors,":[58],"they":[59],"consider":[60],"how":[61,66],"distributed":[62],"is,":[65],"much":[67],"area":[68],"is":[69],"occupied":[70],"interconnect,":[75],"geometric":[78],"properties":[79],"3-D":[81,117],"stacked":[82],"with":[84],"through":[85],"vias":[87],"(TSV)":[88],"as":[89],"vertical":[90],"links.":[91],"We":[92],"use":[93],"ECE":[95],"ECD":[97],"to":[98],"study":[99],"limits":[101],"performance":[103],"under":[104],"different":[105],"distribution,":[107],"power,":[108],"thermal":[109],"cost":[111],"constraints":[112],"various":[114],"2-D":[115],"topologies,":[118],"in":[119],"current":[120],"future":[122],"nodes.":[124]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}