{"id":"https://openalex.org/W2072505467","doi":"https://doi.org/10.1109/vlsisoc.2010.5642697","title":"A design workflow for dynamically reconfigurable multi-FPGA systems","display_name":"A design workflow for dynamically reconfigurable multi-FPGA systems","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2072505467","doi":"https://doi.org/10.1109/vlsisoc.2010.5642697","mag":"2072505467"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2010.5642697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642697","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097667378","display_name":"Alessandro Panel","orcid":null},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alessandro Panel","raw_affiliation_strings":["Computer Science Department, University of Illinois, Chicago, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of Illinois, Chicago, USA","institution_ids":["https://openalex.org/I39422238"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]},{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT","US"],"is_corresponding":false,"raw_author_name":"Marco D. Santambrogio","raw_affiliation_strings":["Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA","Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071090964","display_name":"F. Redaelli","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Redaelli","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090790229","display_name":"Fabio Cancare","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabio Cancare","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione (DEI), Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5097667378"],"corresponding_institution_ids":["https://openalex.org/I39422238"],"apc_list":null,"apc_paid":null,"fwci":0.2497,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.57010697,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"1","issue":null,"first_page":"414","last_page":"419"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.9741252660751343},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.8453031778335571},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8036787509918213},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7857935428619385},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.6852577328681946},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6106040477752686},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6055468916893005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5561180114746094},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5531816482543945},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.48307135701179504},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.4539759159088135},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.4424915909767151},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.43165743350982666},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4191816449165344},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24305367469787598},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10048389434814453},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09298548102378845},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.0855867862701416}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.9741252660751343},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.8453031778335571},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8036787509918213},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7857935428619385},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.6852577328681946},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6106040477752686},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6055468916893005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5561180114746094},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5531816482543945},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.48307135701179504},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.4539759159088135},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.4424915909767151},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.43165743350982666},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4191816449165344},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24305367469787598},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10048389434814453},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09298548102378845},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0855867862701416},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsisoc.2010.5642697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642697","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/572979","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5642697","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W80624900","https://openalex.org/W1484369288","https://openalex.org/W1499156209","https://openalex.org/W1549733891","https://openalex.org/W1989584178","https://openalex.org/W2004951603","https://openalex.org/W2059817063","https://openalex.org/W2068041061","https://openalex.org/W2078174680","https://openalex.org/W2095117703","https://openalex.org/W2099886905","https://openalex.org/W2110469363","https://openalex.org/W2127269626","https://openalex.org/W2148658001","https://openalex.org/W2152373011","https://openalex.org/W2153790296","https://openalex.org/W2294010086","https://openalex.org/W3000171651","https://openalex.org/W4205355374","https://openalex.org/W4236269389","https://openalex.org/W4254806666","https://openalex.org/W6674354551","https://openalex.org/W6683150156"],"related_works":["https://openalex.org/W3103981520","https://openalex.org/W200972441","https://openalex.org/W2038220260","https://openalex.org/W1857140530","https://openalex.org/W1545578515","https://openalex.org/W1544665014","https://openalex.org/W2098458348","https://openalex.org/W2150194641","https://openalex.org/W2128620931","https://openalex.org/W3166559827"],"abstract_inverted_index":{"Multi-FPGA":[0],"systems":[1,98],"(MFS's)":[2],"represent":[3],"a":[4,65,75,126],"promising":[5],"technology":[6],"for":[7,67,118],"various":[8],"applications,":[9],"such":[10],"as":[11],"the":[12,24,30,38,94,113,119,122,131,134],"implementation":[13,95],"of":[14,32,40,86,96,115,121,125,133],"supercomputers":[15],"and":[16,18],"parallel":[17],"computational":[19],"intensive":[20],"emulation":[21],"systems.":[22],"On":[23],"other":[25],"hand,":[26],"dynamic":[27,69,90],"reconfigurability":[28,91],"expands":[29],"possibilities":[31],"traditional":[33],"FPGAs":[34],"by":[35],"providing":[36],"them":[37],"capability":[39],"adapting":[41],"their":[42],"functionality":[43],"while":[44],"still":[45],"running":[46],"to":[47,92,109],"cope":[48],"with":[49,104],"runtime":[50],"environment":[51],"changes.":[52],"These":[53],"two":[54],"research":[55],"directions":[56],"are":[57],"merged":[58],"together":[59],"in":[60],"this":[61,73,110],"work,":[62],"that":[63,128],"describes":[64],"methodology":[66],"designing":[68],"reconfigurable":[70],"MFS's.":[71],"In":[72],"paper":[74],"novel":[76],"MFS":[77],"design":[78],"flow":[79],"has":[80],"been":[81],"described,":[82],"which":[83],"makes":[84],"use":[85],"blocks":[87],"reuse":[88],"through":[89],"make":[93],"large":[97],"feasible":[99],"even":[100],"on":[101],"multi-FPGA":[102],"architectures":[103],"strict":[105],"physical":[106],"constraints.":[107],"Functional":[108],"goal":[111],"is":[112],"development":[114],"an":[116],"algorithm":[117],"extraction":[120],"isomorphic":[123],"structures":[124],"circuit":[127],"extensively":[129],"exploits":[130],"hierarchy":[132],"design.":[135]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
