{"id":"https://openalex.org/W2093832783","doi":"https://doi.org/10.1109/vlsisoc.2010.5642660","title":"Novel input coding technique for high-precision LUT-based multiplication for DSP applications","display_name":"Novel input coding technique for high-precision LUT-based multiplication for DSP applications","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2093832783","doi":"https://doi.org/10.1109/vlsisoc.2010.5642660","mag":"2093832783"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2010.5642660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025809855","display_name":"Pramod Kumar Meher","orcid":"https://orcid.org/0000-0003-0992-1159"},"institutions":[{"id":"https://openalex.org/I3005327000","display_name":"Institute for Infocomm Research","ror":"https://ror.org/053rfa017","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I3005327000","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Pramod Kumar Meher","raw_affiliation_strings":["Department of Embedded Systems, Institute for Infocomm Research, Singapore","Department of Embedded Systems, Institute for Infocomm Research, 1 Fusionopolis Way, Singapore"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, Institute for Infocomm Research, Singapore","institution_ids":["https://openalex.org/I3005327000"]},{"raw_affiliation_string":"Department of Embedded Systems, Institute for Infocomm Research, 1 Fusionopolis Way, Singapore","institution_ids":["https://openalex.org/I3005327000"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5025809855"],"corresponding_institution_ids":["https://openalex.org/I3005327000"],"apc_list":null,"apc_paid":null,"fwci":0.3371,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.58961224,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"201","last_page":"206"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8304608464241028},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.736102819442749},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.6823691129684448},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6196690797805786},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5068314671516418},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.44239112734794617},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4261704683303833},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4134975075721741},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37730181217193604},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3546845018863678},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17123627662658691},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1442461609840393}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8304608464241028},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.736102819442749},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.6823691129684448},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6196690797805786},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5068314671516418},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.44239112734794617},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4261704683303833},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4134975075721741},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37730181217193604},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3546845018863678},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17123627662658691},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1442461609840393},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsisoc.2010.5642660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1965973591","https://openalex.org/W2107115918","https://openalex.org/W2109481485","https://openalex.org/W2128840872","https://openalex.org/W2132897414","https://openalex.org/W2136930455","https://openalex.org/W2151743818","https://openalex.org/W2154807244","https://openalex.org/W2539472691","https://openalex.org/W6728770889"],"related_works":["https://openalex.org/W2089343558","https://openalex.org/W1907116313","https://openalex.org/W2015084332","https://openalex.org/W2125561225","https://openalex.org/W1938177223","https://openalex.org/W2403291794","https://openalex.org/W3009603104","https://openalex.org/W2525693927","https://openalex.org/W1998028015","https://openalex.org/W2382457518"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,22],"present":[4],"a":[5,54],"novel":[6],"input-coding":[7],"scheme":[8,74],"for":[9,29,126],"high-precision":[10],"lookup-table":[11],"(LUT)-based":[12],"implementation":[13],"of":[14,32,50,56,116],"constant":[15],"multiplications":[16],"by":[17,53,96],"input":[18,33,37,72],"operand":[19],"decomposition.":[20],"Besides,":[21],"have":[23],"described":[24],"an":[25],"efficient":[26],"LUT":[27,51,122],"design":[28],"the":[30,36,43,48,60,65,71,87,120],"multiplication":[31],"sub-words":[34],"where":[35],"coding":[38,68,73],"technique":[39,45],"is":[40,108],"combined":[41],"with":[42,64],"odd-multiple-storage":[44],"to":[46,110],"achieve":[47],"reduction":[49],"size":[52],"factor":[55],"~":[57],"4":[58],"over":[59,119],"conventional":[61],"technique.":[62],"Compared":[63],"antisymmetric":[66],"product":[67,118],"(APC)":[69],"scheme,":[70],"involves":[75],"significantly":[76],"less":[77,80],"area":[78],"and":[79,86,94,130],"time":[81],"overheads.":[82],"The":[83,105],"proposed":[84,106],"LUT-multiplier":[85],"existing":[88,121],"one":[89,107],"are":[90],"coded":[91],"in":[92,124],"VHDL":[93],"synthesized":[95],"Synopsys":[97],"Design":[98],"Compiler":[99],"using":[100],"90":[101],"nanometer":[102],"CMOS":[103],"library.":[104],"found":[109],"offer":[111],"more":[112],"than":[113],"28%":[114],"saving":[115],"area-delay":[117],"multiplier,":[123],"average,":[125],"word-sizes":[127],"8,":[128],"16":[129],"32.":[131]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}