{"id":"https://openalex.org/W2089221231","doi":"https://doi.org/10.1109/vlsisoc.2010.5642625","title":"Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper","display_name":"Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2089221231","doi":"https://doi.org/10.1109/vlsisoc.2010.5642625","mag":"2089221231"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2010.5642625","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050421874","display_name":"Paolo Meloni","orcid":"https://orcid.org/0000-0002-8106-4641"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Paolo Meloni","raw_affiliation_strings":["Department of Electric and Electronic Engineering, University of Cagliari, Italy","Dept. of Electric and Electronic Engineering, University of Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081406299","display_name":"Simone Secchi","orcid":"https://orcid.org/0000-0002-8539-1578"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Simone Secchi","raw_affiliation_strings":["Department of Electric and Electronic Engineering, University of Cagliari, Italy","Dept. of Electric and Electronic Engineering, University of Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007761671","display_name":"Luigi Raffo","orcid":"https://orcid.org/0000-0001-9683-009X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luigi Raffo","raw_affiliation_strings":["Department of Electric and Electronic Engineering, University of Cagliari, Italy","Dept. of Electric and Electronic Engineering, University of Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electric and Electronic Engineering, University of Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5050421874"],"corresponding_institution_ids":["https://openalex.org/I172446870"],"apc_list":null,"apc_paid":null,"fwci":0.3561,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6442606,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"43","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8049846291542053},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7927881479263306},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.737851619720459},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7278439998626709},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6407592296600342},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6240013241767883},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5711271166801453},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5182116627693176},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.45250850915908813},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.43545275926589966},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4294193387031555},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.29932859539985657},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07813054323196411}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8049846291542053},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7927881479263306},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.737851619720459},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7278439998626709},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6407592296600342},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6240013241767883},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5711271166801453},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5182116627693176},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.45250850915908813},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.43545275926589966},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4294193387031555},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.29932859539985657},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07813054323196411},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsisoc.2010.5642625","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2010.5642625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unica.it:11584/107299","is_oa":false,"landing_page_url":"http://hdl.handle.net/11584/107299","pdf_url":null,"source":{"id":"https://openalex.org/S4377196293","display_name":"UNICA IRIS Institutional Research Information System (University of Cagliari)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172446870","host_organization_name":"University of Cagliari","host_organization_lineage":["https://openalex.org/I172446870"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1481733864","https://openalex.org/W1861759238","https://openalex.org/W1970939331","https://openalex.org/W2066339098","https://openalex.org/W2072959483","https://openalex.org/W2103127274","https://openalex.org/W2108827571","https://openalex.org/W2121856707","https://openalex.org/W2124495571","https://openalex.org/W2145021036","https://openalex.org/W2156475585","https://openalex.org/W2167985917","https://openalex.org/W2539544045","https://openalex.org/W3137094666","https://openalex.org/W4238549726","https://openalex.org/W4251534053","https://openalex.org/W6667068373"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2340647897","https://openalex.org/W2034458695","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2129154773","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"The":[0,125],"complexity":[1],"of":[2,52,67,87,95],"modern":[3],"interconnect":[4],"architecture":[5,54],"design":[6,104,126,136],"requires":[7],"highly":[8],"accurate":[9],"and":[10,29,118],"rapid":[11],"simulation":[12,31],"environments.":[13],"FPGA-based":[14],"emulators":[15],"have":[16],"been":[17],"proposed":[18],"as":[19],"an":[20,80],"alternative":[21],"to":[22,55,71,100],"software":[23,99],"cycle-accurate":[24],"simulators,":[25],"preserving":[26],"maximum":[27],"accuracy":[28],"reasonable":[30],"times.":[32],"However,":[33],"the":[34,40,53,57,65,103,111,115,119],"potential":[35],"speedup":[36],"is":[37],"reduced":[38],"by":[39,63,129],"time":[41],"overhead":[42],"needed":[43],"for":[44,84],"RTL":[45],"synthesis/implementation.":[46],"This":[47],"paper":[48],"proposes":[49],"runtime":[50],"reconfiguration":[51,113],"push":[56],"hardware":[58,120],"emulation":[59],"one":[60],"step":[61],"further,":[62],"reducing":[64],"number":[66],"FPGA":[68],"implementation":[69],"processes":[70],"be":[72],"run.":[73],"To":[74],"this":[75,77,130],"aim,":[76],"work":[78],"presents":[79],"algorithm":[81],"that":[82,122],"synthesizes,":[83],"a":[85,91,135],"set":[86],"candidate":[88],"architectural":[89],"configurations,":[90],"connection":[92],"topology":[93],"capable":[94],"reconfiguring":[96],"itself":[97],"via":[98],"emulate":[101],"all":[102],"space":[105,137],"points":[106],"under":[107],"evaluation.":[108],"We":[109],"present":[110],"actual":[112],"algorithm,":[114],"CAD":[116],"tools":[117],"mechanisms":[121],"implement":[123],"it.":[124],"capabilities":[127],"provided":[128],"approach":[131],"are":[132],"evaluated":[133],"with":[134],"exploration":[138],"case":[139],"study.":[140]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
