{"id":"https://openalex.org/W2136095062","doi":"https://doi.org/10.1109/vlsisoc.2007.4402504","title":"A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes","display_name":"A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2136095062","doi":"https://doi.org/10.1109/vlsisoc.2007.4402504","mag":"2136095062"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2007.4402504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402504","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031862625","display_name":"Massimo Rovini","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Rovini","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Pisa, Italy","Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101186446","display_name":"Giuseppe Gentile","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Gentile","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Pisa, Italy","Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101982662","display_name":"Francesco Rossi","orcid":"https://orcid.org/0000-0002-1685-097X"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Rossi","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Pisa, Italy","Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046297500","display_name":"Luca Fanucci","orcid":"https://orcid.org/0000-0001-5426-4974"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Fanucci","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Pisa, Italy","Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":null,"apc_paid":null,"fwci":1.4201,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.81871019,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"236","last_page":"241"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10796","display_name":"Cooperative Communication and Network Coding","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7791285514831543},{"id":"https://openalex.org/keywords/soft-decision-decoder","display_name":"Soft-decision decoder","score":0.671536386013031},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6394528746604919},{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.624877393245697},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5476429462432861},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.510941207408905},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5011284351348877},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.49999308586120605},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44086700677871704},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.4376108646392822},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4226396083831787},{"id":"https://openalex.org/keywords/ieee-802","display_name":"IEEE 802","score":0.4169183671474457},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4147852063179016},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4144960641860962},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.412319153547287},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.25019845366477966},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.22781860828399658},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.15907570719718933},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1508629322052002},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.13667824864387512},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1089247465133667}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7791285514831543},{"id":"https://openalex.org/C185588885","wikidata":"https://www.wikidata.org/wiki/Q7553811","display_name":"Soft-decision decoder","level":3,"score":0.671536386013031},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6394528746604919},{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.624877393245697},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5476429462432861},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.510941207408905},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5011284351348877},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.49999308586120605},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44086700677871704},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.4376108646392822},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4226396083831787},{"id":"https://openalex.org/C522090004","wikidata":"https://www.wikidata.org/wiki/Q616245","display_name":"IEEE 802","level":3,"score":0.4169183671474457},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4147852063179016},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4144960641860962},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.412319153547287},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25019845366477966},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.22781860828399658},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.15907570719718933},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1508629322052002},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.13667824864387512},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1089247465133667},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsisoc.2007.4402504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402504","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},{"id":"pmh:oai:arpi.unipi.it:11568/111868","is_oa":false,"landing_page_url":"http://hdl.handle.net/11568/111868","pdf_url":null,"source":{"id":"https://openalex.org/S4377196265","display_name":"CINECA IRIS Institutial research information system (University of Pisa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I108290504","host_organization_name":"University of Pisa","host_organization_lineage":["https://openalex.org/I108290504"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1480903969","https://openalex.org/W1518608438","https://openalex.org/W1572884776","https://openalex.org/W1573665190","https://openalex.org/W1966336366","https://openalex.org/W2046091144","https://openalex.org/W2102815459","https://openalex.org/W2107301532","https://openalex.org/W2109317804","https://openalex.org/W2117447277","https://openalex.org/W2126419525","https://openalex.org/W2128765501","https://openalex.org/W2133468827","https://openalex.org/W2162811899","https://openalex.org/W2535550790","https://openalex.org/W3121094298","https://openalex.org/W4242135463","https://openalex.org/W6675013778","https://openalex.org/W6678839936"],"related_works":["https://openalex.org/W2903058006","https://openalex.org/W2102374550","https://openalex.org/W2353338231","https://openalex.org/W2035769530","https://openalex.org/W2064674583","https://openalex.org/W2077272551","https://openalex.org/W4299647765","https://openalex.org/W2388275429","https://openalex.org/W1979159634","https://openalex.org/W2785398129"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,7,50,105],"scalable":[4],"architecture":[5,25],"of":[6,30,59,76,91,112],"decoder":[8,17,45],"for":[9,94,134],"IEEE":[10],"802.11n":[11],"low-density":[12],"parity-check":[13],"(LDPC)":[14],"codes.":[15],"The":[16,44,115],"runs":[18],"the":[19,42,57,68,74,77,83,89,110,113,129,137,146],"layered":[20],"decoding":[21],"algorithm":[22],"and":[23,49,80,145],"its":[24,60],"is":[26,62,132],"arranged":[27],"in":[28,41,47,64],"clusters":[29],"serial":[31],"functional":[32],"units,":[33,85],"which":[34],"are":[35],"configured":[36],"to":[37,54,66,73,103,142],"process":[38],"all":[39],"codes":[40],"standard.":[43],"works":[46],"pipeline,":[48],"very":[51,106],"effective":[52],"technique":[53],"re-":[55],"arrange":[56],"sequence":[58,90],"elaborations":[61],"proposed":[63,130],"order":[65,75],"minimize":[67],"iteration":[69],"latency;":[70],"this":[71],"relates":[72],"messages":[78],"input":[79],"output":[81],"by":[82],"processing":[84],"as":[86,88],"well":[87],"layers":[92],"followed":[93],"decoding.":[95],"Moreover,":[96],"memory":[97],"optimization":[98],"techniques":[99],"have":[100],"been":[101],"applied":[102],"get":[104],"efficient":[107],"partitioning,":[108],"allowing":[109],"pipeline":[111],"operations.":[114],"synthesis":[116],"on":[117],"65":[118],"nm":[119],"CMOS":[120],"technology":[121],"with":[122],"low-power":[123],"standard-":[124],"cell":[125],"library,":[126],"shows":[127],"that":[128],"design":[131],"suitable":[133],"portable":[135],"devices,":[136],"throughput":[138],"ranging":[139],"from":[140],"136":[141],"355":[143],"Mbps,":[144],"power":[147],"consumption":[148],"being":[149],"below":[150],"185":[151],"mW.":[152]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}