{"id":"https://openalex.org/W2142914495","doi":"https://doi.org/10.1109/vlsisoc.2007.4402495","title":"Dynamic gates with hysteresis and configurable noise tolerance","display_name":"Dynamic gates with hysteresis and configurable noise tolerance","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2142914495","doi":"https://doi.org/10.1109/vlsisoc.2007.4402495","mag":"2142914495"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2007.4402495","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402495","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019487332","display_name":"Krishna Santhanam","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishna Santhanam","raw_affiliation_strings":["Electrical and Computer Engineering, University of Utah, USA","[Electrical and Computer Engineering, University of Utah, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Utah, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"[Electrical and Computer Engineering, University of Utah, USA]","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113695022","display_name":"Kenneth S. Stevens","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kenneth S. Stevens","raw_affiliation_strings":["Electrical and Computer Engineering, University of Utah, USA","[Electrical and Computer Engineering, University of Utah, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Utah, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"[Electrical and Computer Engineering, University of Utah, USA]","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25922231,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e80 d","issue":null,"first_page":"184","last_page":"189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.7098448276519775},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7078024744987488},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.7074611186981201},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6338257789611816},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.6282354593276978},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6277711391448975},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6111292839050293},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.59842449426651},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5767170190811157},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5070922374725342},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.49638229608535767},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4519370496273041},{"id":"https://openalex.org/keywords/hysteresis","display_name":"Hysteresis","score":0.4386316239833832},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4169937074184418},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41129976511001587},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.40650370717048645},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3580583930015564},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.30351585149765015},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3009740710258484},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2535313069820404},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15963298082351685},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1273667812347412}],"concepts":[{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.7098448276519775},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7078024744987488},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.7074611186981201},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6338257789611816},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.6282354593276978},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6277711391448975},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6111292839050293},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.59842449426651},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5767170190811157},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5070922374725342},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.49638229608535767},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4519370496273041},{"id":"https://openalex.org/C123299182","wikidata":"https://www.wikidata.org/wiki/Q190837","display_name":"Hysteresis","level":2,"score":0.4386316239833832},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4169937074184418},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41129976511001587},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.40650370717048645},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3580583930015564},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.30351585149765015},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3009740710258484},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2535313069820404},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15963298082351685},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1273667812347412},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsisoc.2007.4402495","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402495","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.143.2779","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.2779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.utah.edu/~kstevens/docs/ifip-vlsi07.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8100000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W77238993","https://openalex.org/W1514444429","https://openalex.org/W1565299145","https://openalex.org/W1823434954","https://openalex.org/W1837287653","https://openalex.org/W2012173826","https://openalex.org/W2029005287","https://openalex.org/W2038425387","https://openalex.org/W2088115909","https://openalex.org/W2098061796","https://openalex.org/W2107003620","https://openalex.org/W2125451720","https://openalex.org/W2133467019","https://openalex.org/W2153317824","https://openalex.org/W2160823654","https://openalex.org/W6638563171","https://openalex.org/W6660061292","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W2991771859","https://openalex.org/W2184285466","https://openalex.org/W2802423915","https://openalex.org/W1996043106","https://openalex.org/W1668918857","https://openalex.org/W2529167390","https://openalex.org/W3012469827","https://openalex.org/W2058400468","https://openalex.org/W2158157809","https://openalex.org/W2142914495"],"abstract_inverted_index":{"Dynamic":[0],"logic":[1,31,36,45,113],"can":[2,136],"provide":[3],"significant":[4],"performance":[5,130],"and":[6,69,86,102,110],"power":[7],"benefit":[8],"compared":[9],"to":[10,55,116],"implementations":[11],"using":[12,145],"static":[13],"gates.":[14],"Unfortunately":[15],"dynamic":[16,35,49,57,62,92,133],"gates":[17,63,135],"have":[18],"traditionally":[19],"suffered":[20],"from":[21],"low":[22],"noise":[23,72,143],"margins,":[24],"which":[25],"limits":[26],"their":[27],"reliability.":[28],"A":[29],"new":[30],"family,":[32],"called":[33],"complementary":[34],"(CDL),":[37],"is":[38,53],"presented.":[39],"CDL":[40,60,109,146],"replaces":[41],"the":[42,80,84,88,91,97,129],"standard":[43],"keeper":[44,50],"with":[46,64],"a":[47,117],"dual":[48],"gate":[51,58],"that":[52,128],"applicable":[54],"all":[56],"structures.":[59,147],"provides":[61],"two":[65,76],"novel":[66],"characteristics:":[67],"hysteresis":[68],"arbitrarily":[70],"configurable":[71],"margins.":[73],"However,":[74],"these":[75],"benefits":[77],"come":[78],"at":[79],"cost":[81],"of":[82,90,108,122,132],"reducing":[83],"gain":[85],"increasing":[87],"energy":[89],"gate.":[93],"This":[94],"paper":[95],"compares":[96],"noise,":[98],"energy,":[99],"performance,":[100],"gain,":[101],"total":[103],"transistor":[104],"width":[105],"trade-":[106],"offs":[107],"three":[111],"other":[112],"families":[114],"applied":[115],"65nm":[118],"cell":[119],"library":[120],"consisting":[121],"23":[123],"functions.":[124],"The":[125],"results":[126],"show":[127],"advantages":[131],"domino":[134],"be":[137],"maintained":[138],"while":[139],"providing":[140],"significantly":[141],"enhanced":[142],"margins":[144]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
