{"id":"https://openalex.org/W2119419060","doi":"https://doi.org/10.1109/vlsisoc.2007.4402484","title":"Computing and design for software and silicon manufacturing","display_name":"Computing and design for software and silicon manufacturing","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2119419060","doi":"https://doi.org/10.1109/vlsisoc.2007.4402484","mag":"2119419060"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2007.4402484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065985032","display_name":"Davide Pandini","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Davide Pandini","raw_affiliation_strings":["Central CAD and Design Solutions, STMicroelectronics, Agrate, Italy","STMicroelectronics, Central CAD and Design Solutions, Agrate Brianza 20041, Italy"],"affiliations":[{"raw_affiliation_string":"Central CAD and Design Solutions, STMicroelectronics, Agrate, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Central CAD and Design Solutions, Agrate Brianza 20041, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047102959","display_name":"Giuseppe Desoli","orcid":"https://orcid.org/0000-0002-3901-0770"},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Desoli","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Cornaredo, Italy","STMicroelectronics, Advanced System Technology, Cornaredo, 20010 Italy"],"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Cornaredo, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Advanced System Technology, Cornaredo, 20010 Italy","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052250583","display_name":"A. Cremonesi","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Alessandro Cremonesi","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Agrate, Italy","STMicroelectronics, Advanced System Technology, Agrate Brianza, 20041 Italy"],"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Agrate, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Advanced System Technology, Agrate Brianza, 20041 Italy","institution_ids":["https://openalex.org/I131827901"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065985032"],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":1.0537,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79430932,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"122","last_page":"127"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8377540111541748},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6009133458137512},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.5924515128135681},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4722682237625122},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4622570872306824},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4546029269695282},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4385102093219757},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4375956058502197},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26135432720184326},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14971613883972168},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1331196129322052}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8377540111541748},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6009133458137512},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.5924515128135681},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4722682237625122},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4622570872306824},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4546029269695282},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4385102093219757},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4375956058502197},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26135432720184326},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14971613883972168},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1331196129322052},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsisoc.2007.4402484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4000000059604645}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310207","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1971495518","https://openalex.org/W1977237480","https://openalex.org/W2053901328","https://openalex.org/W2100344939","https://openalex.org/W2124313718","https://openalex.org/W2131862714","https://openalex.org/W6643197073","https://openalex.org/W6674862444"],"related_works":["https://openalex.org/W2170833250","https://openalex.org/W1545209567","https://openalex.org/W4234416624","https://openalex.org/W2549099758","https://openalex.org/W1608282732","https://openalex.org/W2183741735","https://openalex.org/W3148906596","https://openalex.org/W1996963888","https://openalex.org/W411986334","https://openalex.org/W2184952494"],"abstract_inverted_index":{"An":[0],"increasing":[1],"demand":[2],"for":[3,6,11,49,61,126],"higher":[4],"performance,":[5,82],"lower":[7],"power":[8,83],"density,":[9],"and":[10,56,58,65,85,96,131,134],"greatly":[12],"expanded":[13],"functionalities":[14],"will":[15],"determine":[16],"radical":[17],"changes":[18],"in":[19,71],"the":[20,35,78,89,92,98,113,123,127],"future":[21],"computing":[22,94,129],"architectures.":[23],"These":[24],"widely":[25],"acknowledged":[26],"emerging":[27,124],"trends":[28],"are":[29,68],"however":[30],"insufficient":[31],"to":[32],"address":[33],"all":[34],"challenges":[36,125],"introduced":[37],"by":[38,111],"advanced":[39],"silicon":[40,99,138],"nanometer":[41],"technologies.":[42],"It":[43],"is":[44],"well":[45],"known":[46],"that":[47,110],"manufacturability":[48],"high":[50],"yield,":[51],"along":[52],"with":[53,137],"design":[54,79],"productivity":[55],"predictability":[57],"system":[59,133],"reconfigurability":[60],"reduced":[62],"NRE":[63],"costs":[64],"faster":[66],"time-to-market,":[67],"major":[69],"problems":[70],"gigascale":[72],"SoC":[73],"design.":[74],"Therefore,":[75],"only":[76],"focusing":[77],"efforts":[80],"on":[81],"consumption,":[84],"throughput":[86],"can":[87],"hinder":[88],"potentials":[90],"of":[91,115,120],"new":[93,128],"architectures":[95],"limit":[97],"yield.":[100],"In":[101],"this":[102],"paper,":[103],"we":[104],"introduce":[105],"an":[106],"innovative":[107],"architecture-to-silicon":[108],"platform":[109],"exploiting":[112],"concept":[114],"regularity":[116],"at":[117],"different":[118],"levels":[119],"abstraction":[121],"addresses":[122],"architectures,":[130],"links":[132],"architecture":[135],"definition":[136],"fabrication.":[139]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
