{"id":"https://openalex.org/W2014840902","doi":"https://doi.org/10.1109/vlsisoc.2007.4402483","title":"Transistor level automatic layout generator for non-complementary CMOS cells","display_name":"Transistor level automatic layout generator for non-complementary CMOS cells","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2014840902","doi":"https://doi.org/10.1109/vlsisoc.2007.4402483","mag":"2014840902"},"language":"en","primary_location":{"id":"doi:10.1109/vlsisoc.2007.4402483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023900574","display_name":"Adriel Ziesemer","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Adriel Ziesemer","raw_affiliation_strings":["Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brasil","Ricardo Reis Instituto de Informatica, Universidade Federal do Rio Grande do Sul (UFRGS), Av. Bento Goncalves, 9500. Bloco IV. CP 91501-970. Porto Alegre/RS, Brasil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brasil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Ricardo Reis Instituto de Informatica, Universidade Federal do Rio Grande do Sul (UFRGS), Av. Bento Goncalves, 9500. Bloco IV. CP 91501-970. Porto Alegre/RS, Brasil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017218053","display_name":"Cristiano Lazzar","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Cristiano Lazzar","raw_affiliation_strings":["Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brasil","Ricardo Reis Instituto de Informatica, Universidade Federal do Rio Grande do Sul (UFRGS), Av. Bento Goncalves, 9500. Bloco IV. CP 91501-970. Porto Alegre/RS, Brasil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brasil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Ricardo Reis Instituto de Informatica, Universidade Federal do Rio Grande do Sul (UFRGS), Av. Bento Goncalves, 9500. Bloco IV. CP 91501-970. Porto Alegre/RS, Brasil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":4.4895,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.94880131,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"116","last_page":"121"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9233850240707397},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6847047805786133},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6277838945388794},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6198807954788208},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5990197658538818},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5897774696350098},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5250679850578308},{"id":"https://openalex.org/keywords/rework","display_name":"Rework","score":0.5089199542999268},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.49979257583618164},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.45344170928001404},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4407602548599243},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42564254999160767},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4147108793258667},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32878512144088745},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27048853039741516},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.264147013425827},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24249771237373352},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22571900486946106},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2147488296031952},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1851450502872467},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17177814245224}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9233850240707397},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6847047805786133},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6277838945388794},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6198807954788208},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5990197658538818},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5897774696350098},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5250679850578308},{"id":"https://openalex.org/C2776543023","wikidata":"https://www.wikidata.org/wiki/Q2147046","display_name":"Rework","level":2,"score":0.5089199542999268},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.49979257583618164},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.45344170928001404},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4407602548599243},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42564254999160767},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4147108793258667},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32878512144088745},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27048853039741516},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.264147013425827},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24249771237373352},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22571900486946106},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2147488296031952},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1851450502872467},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17177814245224},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsisoc.2007.4402483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsisoc.2007.4402483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IFIP International Conference on Very Large Scale Integration","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1494124775","https://openalex.org/W1531753705","https://openalex.org/W1987067207","https://openalex.org/W2004115473","https://openalex.org/W2022218016","https://openalex.org/W2043780523","https://openalex.org/W2046812935","https://openalex.org/W2063553865","https://openalex.org/W2124095578","https://openalex.org/W2128540183","https://openalex.org/W2153981889","https://openalex.org/W2167441238","https://openalex.org/W2275304190","https://openalex.org/W4230970194","https://openalex.org/W4241865974","https://openalex.org/W4250738681"],"related_works":["https://openalex.org/W2111251553","https://openalex.org/W3148693912","https://openalex.org/W2120549874","https://openalex.org/W2156069452","https://openalex.org/W4210841712","https://openalex.org/W2045146060","https://openalex.org/W2583707817","https://openalex.org/W2115934614","https://openalex.org/W2142651762","https://openalex.org/W2128606704"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,30,52,82],"tool":[4,25],"that":[5,59,100],"makes":[6],"it":[7],"possible":[8],"to":[9,40,94,106],"generate":[10],"full":[11],"layouts":[12,104],"of":[13,63,66,72],"CMOS":[14],"cells":[15,28,116],"from":[16],"its":[17],"transistor":[18,46,53],"level":[19],"netlist":[20],"in":[21],"SPICE":[22],"format.":[23],"The":[24,76,96,109],"generates":[26],"the":[27,61,64,70,73],"under":[29],"linear":[31],"matrix":[32],"(1I))":[33],"similar":[34],"layout":[35],"style":[36],"and":[37,48,69,85],"is":[38,92],"able":[39],"support":[41],"unrestricted":[42],"circuit":[43,77],"structures,":[44],"continuous":[45],"sizing":[47],"folding.":[49],"It":[50],"features":[51],"placement":[54],"algorithm":[55],"for":[56,115],"width":[57],"reduction":[58,62],"aims":[60],"number":[65],"diffusion":[67],"gaps":[68],"wirelength":[71],"internal":[74],"connections.":[75],"nets":[78],"are":[79],"routed":[80],"using":[81],"negotiation-based":[83],"algorithm,":[84],"an":[86],"Integer":[87],"Linear":[88],"Programming":[89],"(ILP)":[90],"solver":[91],"used":[93],"compaction.":[95],"experimental":[97],"results":[98],"show":[99],"our":[101],"methodology":[102],"produces":[103],"competitive":[105],"exact":[107],"methods.":[108],"runtimes":[110],"were":[111],"kept":[112],"low":[113],"even":[114],"with":[117],"more":[118],"than":[119],"30":[120],"transistors.":[121]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2026-08-11T07:18:39.950985","created_date":"2025-10-10T00:00:00"}
