{"id":"https://openalex.org/W7137952037","doi":"https://doi.org/10.1109/vlsid68508.2026.00098","title":"A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology","display_name":"A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology","publication_year":2026,"publication_date":"2026-01-03","ids":{"openalex":"https://openalex.org/W7137952037","doi":"https://doi.org/10.1109/vlsid68508.2026.00098"},"language":null,"primary_location":{"id":"doi:10.1109/vlsid68508.2026.00098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00098","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101747519","display_name":"Anamika Sharma","orcid":"https://orcid.org/0000-0003-1342-3523"},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anamika Sharma","raw_affiliation_strings":["STMicroelectronics,Greater Noida,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Greater Noida,India","institution_ids":["https://openalex.org/I4210094169"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5099842366","display_name":"Luv Pandey","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Luv Pandey","raw_affiliation_strings":["STMicroelectronics,Greater Noida,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Greater Noida,India","institution_ids":["https://openalex.org/I4210094169"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112934794","display_name":"Paras Garg","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Paras Garg","raw_affiliation_strings":["STMicroelectronics,Greater Noida,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Greater Noida,India","institution_ids":["https://openalex.org/I4210094169"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091782947","display_name":"Rajesh Zele","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajesh Zele","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34750911,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"496","last_page":"500"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.853600025177002,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.853600025177002,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.05339999869465828,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.03229999914765358,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5220999717712402},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.3637000024318695},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.31349998712539673},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.3095000088214874},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.29330000281333923},{"id":"https://openalex.org/keywords/measure","display_name":"Measure (data warehouse)","score":0.2703000009059906}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5324000120162964},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5220999717712402},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.447299987077713},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.3637000024318695},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3206000030040741},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.31349998712539673},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3095000088214874},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.29330000281333923},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2833999991416931},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.2703000009059906},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26739999651908875},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26669999957084656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25600001215934753},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2522999942302704},{"id":"https://openalex.org/C132094186","wikidata":"https://www.wikidata.org/wiki/Q641585","display_name":"Clutter","level":3,"score":0.2506999969482422}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsid68508.2026.00098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00098","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7861765623092651,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1526838648","https://openalex.org/W1648307515","https://openalex.org/W2079825871","https://openalex.org/W2095089117","https://openalex.org/W2097216498","https://openalex.org/W2565240407","https://openalex.org/W2593067874","https://openalex.org/W2621562453","https://openalex.org/W2744970705","https://openalex.org/W2897458229","https://openalex.org/W2899600101","https://openalex.org/W2911447470","https://openalex.org/W2921260700","https://openalex.org/W2922215933","https://openalex.org/W3043637203","https://openalex.org/W3205151931","https://openalex.org/W4205594724","https://openalex.org/W4399997019","https://openalex.org/W4400232634","https://openalex.org/W4411727596"],"related_works":[],"abstract_inverted_index":{"Noise-shaping":[0],"SAR":[1,19,33,57,67,83,135],"ADC":[2,7,34,51,58,84,100,136,159,182],"represents":[3],"a":[4,36,55,89,105,132,143,147,162,167,175],"promising":[5],"hybrid":[6],"architecture":[8,43],"that":[9],"combines":[10],"the":[11,16,24,74,78,82,113,138],"benefits":[12],"of":[13,18,26,38,131,170,178,186],"noiseshaping":[14],"with":[15,40,137,166],"efficiency":[17],"conversion.":[20],"This":[21,93],"paper":[22],"presents":[23],"design":[25,76],"an":[27,45,125,184],"8-bit,":[28],"40":[29,109,148],"MHz":[30,149],"bandwidth":[31,150],"noise-shaping":[32,66],"employing":[35],"Cascade":[37],"Integrators":[39],"Feed-Forward":[41],"(CIFF)":[42],"featuring":[44],"active":[46,65],"loop":[47],"filter.":[48],"The":[49,158,181],"core":[50],"is":[52],"implemented":[53],"as":[54],"sub-ranging":[56],"to":[59,117],"increase":[60,111],"conversion":[61,114],"speed.":[62],"Unlike":[63],"traditional":[64],"ADCs,":[68],"which":[69],"perform":[70],"residue":[71,79,91,97],"amplification":[72,98],"sequentially,":[73],"proposed":[75,139],"decouples":[77],"voltage":[80],"from":[81,161],"and":[85,99],"samples":[86],"it":[87],"onto":[88],"dedicated":[90],"capacitor.":[92],"approach":[94],"enables":[95],"simultaneous":[96],"input":[101],"sampling,":[102],"resulting":[103,173],"in":[104,112,146,174],"<tex":[106,152,187],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[107,153,188],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\sim":[108],"{\\%}$</tex>":[110],"rate":[115],"compared":[116],"conventional":[118],"architectures.":[119],"Postlayout":[120],"simulation":[121],"results,":[122],"based":[123],"on":[124],"18":[126],"nm":[127],"FD-SOI":[128],"CMOS":[129],"implementation":[130],"partially":[133],"loop-unrolled":[134],"loop-filter":[140],"architecture,":[141],"achieve":[142],"57dB":[144],"SNDR":[145],"at":[151],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$320":[154],"\\text{MS}":[155],"/":[156],"\\mathrm{s}$</tex>.":[157],"operates":[160],"1":[163],"V":[164],"supply":[165],"power":[168],"consumption":[169],"2.15":[171],"mW,":[172],"Schreier":[176],"FoM":[177],"160":[179],"dB.":[180],"occupies":[183],"area":[185],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$150":[189],"\\mu":[190,194],"\\mathrm{m}":[191],"\\times":[192],"100":[193],"\\mathrm{m}$</tex>.":[195]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-03-18T00:00:00"}
