{"id":"https://openalex.org/W7137939121","doi":"https://doi.org/10.1109/vlsid68508.2026.00028","title":"PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells","display_name":"PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells","publication_year":2026,"publication_date":"2026-01-03","ids":{"openalex":"https://openalex.org/W7137939121","doi":"https://doi.org/10.1109/vlsid68508.2026.00028"},"language":null,"primary_location":{"id":"doi:10.1109/vlsid68508.2026.00028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019957161","display_name":"Mohammad Rehan Akhtar","orcid":"https://orcid.org/0000-0001-8927-8655"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mohammad Rehan Akhtar","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5129676482","display_name":"Zia Abbas","orcid":null},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Zia Abbas","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019957161"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.90320191,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"84"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.6103000044822693,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.6103000044822693,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.13830000162124634,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.11819999665021896,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5166000127792358},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45820000767707825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3707999885082245},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.3246999979019165},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.27559998631477356}],"concepts":[{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5166000127792358},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5157999992370605},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45820000767707825},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4514000117778778},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4438999891281128},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.38839998841285706},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3707999885082245},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.35339999198913574},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.34529998898506165},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3246999979019165},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3172000050544739},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.27559998631477356},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.26409998536109924},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.2515000104904175}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsid68508.2026.00028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.58799809217453,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1968204888","https://openalex.org/W2115834537","https://openalex.org/W2806210915","https://openalex.org/W2911591439","https://openalex.org/W3091131165","https://openalex.org/W4251306844","https://openalex.org/W4293243546","https://openalex.org/W4310256192","https://openalex.org/W4380894245","https://openalex.org/W4382318057","https://openalex.org/W4385286884","https://openalex.org/W4390187418","https://openalex.org/W4400231453","https://openalex.org/W4401414040","https://openalex.org/W4403479338"],"related_works":[],"abstract_inverted_index":{"FinFET":[0,114],"technology":[1,18],"has":[2],"emerged":[3],"as":[4,25],"a":[5,26,71,78,142],"solution":[6],"to":[7,29,63,130,148],"mitigate":[8],"the":[9,84],"short-channel":[10],"effects":[11],"in":[12,51,156],"CMOS":[13],"technology.":[14],"However,":[15],"with":[16],"continued":[17],"scaling,":[19],"leakage":[20,46,66,91],"power":[21,31,92,154],"is":[22],"now":[23],"emerging":[24],"primary":[27],"contributor":[28],"total":[30],"consumption.":[32],"Additionally,":[33],"aging":[34,89],"effects,":[35,100],"compounded":[36],"by":[37,101],"process,":[38],"voltage,":[39],"and":[40,55,90,98,110,126,134,144],"temperature":[41],"(PVT)":[42],"variations,":[43],"significantly":[44],"degrade":[45],"behavior":[47],"over":[48],"time,":[49],"resulting":[50],"high":[52],"data":[53],"variance":[54],"posing":[56],"challenges":[57],"for":[58,152],"conventional":[59],"machine":[60,73],"learning":[61,74,136],"models":[62],"generalize":[64],"aging-induced":[65],"trends.":[67],"This":[68],"paper":[69],"proposes":[70],"physics-informed":[72],"architecture":[75],"based":[76],"on":[77,107],"deaggregation-based":[79],"methodology":[80],"that":[81],"effectively":[82],"captures":[83],"complex,":[85],"non-linear":[86],"relationship":[87],"between":[88],"across":[93],"PVT,":[94],"incorporating":[95],"both":[96],"NBTI":[97],"HCI":[99],"leveraging":[102],"pattern-oriented":[103],"knowledge.":[104],"Experimental":[105],"evaluations":[106],"7":[108],"nm":[109,112],"10":[111],"high-performance":[113],"standard":[115],"cells":[116],"demonstrate":[117],"mean":[118],"absolute":[119],"percentage":[120],"error":[121],"(MAPE)":[122],"improvements":[123],"of":[124],"52.71%":[125],"54.44%,":[127],"respectively,":[128],"compared":[129],"state-of-the-art":[131],"standalone":[132],"boosting":[133],"deep":[135],"models.":[137],"The":[138],"proposed":[139],"method":[140],"presents":[141],"robust":[143],"computationally":[145],"efficient":[146],"alternative":[147],"traditional":[149],"simulation-based":[150],"approaches":[151],"agingaware":[153],"estimation":[155],"digital":[157],"circuit":[158],"design.":[159]},"counts_by_year":[],"updated_date":"2026-03-20T20:47:17.329874","created_date":"2026-03-18T00:00:00"}
