{"id":"https://openalex.org/W7137982731","doi":"https://doi.org/10.1109/vlsid68508.2026.00027","title":"ASIC Design for a Hybrid Approximate Floating-Point Adder with Enhanced Carry Prediction Logic","display_name":"ASIC Design for a Hybrid Approximate Floating-Point Adder with Enhanced Carry Prediction Logic","publication_year":2026,"publication_date":"2026-01-03","ids":{"openalex":"https://openalex.org/W7137982731","doi":"https://doi.org/10.1109/vlsid68508.2026.00027"},"language":null,"primary_location":{"id":"doi:10.1109/vlsid68508.2026.00027","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00027","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5127914255","display_name":"Sridhar C","orcid":null},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sridhar C","raw_affiliation_strings":["National Institute of Technology Puducherry,VEDIC Laboratory,Department of Electronics and Communication Engineering,Karaikal,India"],"raw_orcid":"https://orcid.org/0009-0003-1298-6399","affiliations":[{"raw_affiliation_string":"National Institute of Technology Puducherry,VEDIC Laboratory,Department of Electronics and Communication Engineering,Karaikal,India","institution_ids":["https://openalex.org/I11880225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071372208","display_name":"Aniruddha Kanhe","orcid":"https://orcid.org/0000-0002-3674-2968"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aniruddha Kanhe","raw_affiliation_strings":["National Institute of Technology Puducherry,VEDIC Laboratory,Department of Electronics and Communication Engineering,Karaikal,India"],"raw_orcid":"https://orcid.org/0000-0002-3674-2968","affiliations":[{"raw_affiliation_string":"National Institute of Technology Puducherry,VEDIC Laboratory,Department of Electronics and Communication Engineering,Karaikal,India","institution_ids":["https://openalex.org/I11880225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I11880225"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27962617,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.6761999726295471,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.6761999726295471,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.09489999711513519,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.08959999680519104,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6809999942779541},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4661000072956085},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.42969998717308044},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.33809998631477356},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.329800009727478},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.28529998660087585}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6809999942779541},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.629800021648407},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4661000072956085},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.42969998717308044},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33809998631477356},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.329800009727478},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3165000081062317},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3138999938964844},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.28529998660087585},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2721000015735626},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.26750001311302185},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.26269999146461487},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.259799987077713},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.2549999952316284},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2533999979496002},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsid68508.2026.00027","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid68508.2026.00027","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.625115156173706}],"awards":[{"id":"https://openalex.org/G2571784506","display_name":null,"funder_award_id":"EE\u20109/2/2021\u2010R&D\u2010E","funder_id":"https://openalex.org/F4320325255","funder_display_name":"Ministry of Electronics and Information technology"}],"funders":[{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2042456747","https://openalex.org/W2052363354","https://openalex.org/W2079986413","https://openalex.org/W2135089667","https://openalex.org/W2204310803","https://openalex.org/W2559460803","https://openalex.org/W2801205959","https://openalex.org/W2891540872","https://openalex.org/W2916566087","https://openalex.org/W2919795555","https://openalex.org/W2953682625","https://openalex.org/W2982216783","https://openalex.org/W2985336152","https://openalex.org/W3011299928","https://openalex.org/W3037505396","https://openalex.org/W3136258898","https://openalex.org/W3157484444","https://openalex.org/W3195784889","https://openalex.org/W3196589408","https://openalex.org/W4400198901"],"related_works":[],"abstract_inverted_index":{"Approximate":[0,14],"computing":[1],"plays":[2],"a":[3,39,55,126],"vital":[4],"role":[5],"in":[6,68,81,85,90,97,110],"accelerating":[7],"large-scale":[8],"data":[9],"processing":[10,148],"for":[11,23,33,48,141],"error-resilient":[12],"applications.":[13],"adders":[15],"are":[16],"designed":[17],"to":[18,59,102],"trade":[19],"off":[20],"computational":[21],"accuracy":[22,62],"reduced":[24],"delay":[25],"and":[26,95,116,149],"lower":[27,113],"hardware":[28,65],"complexity,":[29],"making":[30,138],"them":[31],"well-suited":[32],"such":[34],"domains.":[35],"This":[36],"paper":[37],"presents":[38],"novel":[40],"approximate":[41,104],"adder":[42,47,53],"integrated":[43],"into":[44],"single-precision":[45],"floatingpoint":[46],"mantissa":[49],"addition.":[50],"The":[51],"proposed":[52,74],"employs":[54],"carry":[56,128],"prediction":[57,129],"logic":[58],"improve":[60],"the":[61,73,132],"without":[63],"increasing":[64],"cost.":[66],"Implemented":[67],"SCL":[69],"180nm":[70],"CMOS":[71],"technology,":[72],"design":[75],"achieves":[76],"average":[77],"improvements":[78],"of":[79],"50.56%":[80],"standard":[82],"deviation,":[83],"59.66%":[84],"mean":[86,92,98],"absolute":[87],"error,":[88],"56.13%":[89],"normalized":[91],"error":[93,100,130],"distance,":[94],"81.40%":[96],"square":[99],"compared":[101],"existing":[103],"adders.":[105],"It":[106],"further":[107],"demonstrates":[108],"10.16%":[109],"delay,":[111],"12.7%":[112],"power":[114],"consumption":[115],"45.5%":[117],"fewer":[118],"gates":[119],"than":[120],"an":[121],"accurate":[122],"reference":[123],"adder.":[124],"With":[125],"6.68%":[127],"rate,":[131],"architecture":[133],"delivers":[134],"balanced":[135],"accuracy-speed-efficiency":[136],"trade-offs,":[137],"it":[139],"promising":[140],"high-speed,":[142],"low-power":[143],"VLSI":[144],"applications":[145],"like":[146],"signal":[147],"machine":[150],"learning":[151],"accelerators.":[152]},"counts_by_year":[],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2026-03-18T00:00:00"}