{"id":"https://openalex.org/W2166769158","doi":"https://doi.org/10.1109/vlsid.2012.86","title":"A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip","display_name":"A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2166769158","doi":"https://doi.org/10.1109/vlsid.2012.86","mag":"2166769158"},"language":"en","primary_location":{"id":"doi:10.1109/vlsid.2012.86","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2012.86","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 25th International Conference on VLSI Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077422345","display_name":"Praveen Salihundam","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Praveen Salihundam","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067178208","display_name":"M. A. Khan","orcid":"https://orcid.org/0000-0002-4219-2149"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mohammed Asadullah Khan","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090001638","display_name":"Shailendra Jain","orcid":"https://orcid.org/0000-0002-3391-1711"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shailendra Jain","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081186735","display_name":"Yatin Hoskote","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yatin Hoskote","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024748519","display_name":"Satish Yada","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Satish Yada","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100974612","display_name":"Shasi Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shasi Kumar","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vasantha Erraguntla","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram Vangal","orcid":"https://orcid.org/0000-0003-1548-9876"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Vangal","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nitin Borkar","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23970743,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"292","last_page":"297"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9909999966621399,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tile","display_name":"Tile","score":0.7766042351722717},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.6462055444717407},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6293357610702515},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.610053539276123},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5942355394363403},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5850816965103149},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5709962844848633},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5033542513847351},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.48093146085739136},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.47620925307273865},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.45439910888671875},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.43213149905204773},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4286077618598938},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27772313356399536},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27468034625053406},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2556854486465454},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17387375235557556},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09934628009796143}],"concepts":[{"id":"https://openalex.org/C2780728851","wikidata":"https://www.wikidata.org/wiki/Q468402","display_name":"Tile","level":2,"score":0.7766042351722717},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.6462055444717407},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6293357610702515},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.610053539276123},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5942355394363403},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5850816965103149},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5709962844848633},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5033542513847351},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.48093146085739136},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.47620925307273865},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45439910888671875},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.43213149905204773},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4286077618598938},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27772313356399536},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27468034625053406},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2556854486465454},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17387375235557556},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09934628009796143},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsid.2012.86","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2012.86","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 25th International Conference on VLSI Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W2001894083","https://openalex.org/W2006500015","https://openalex.org/W2057032191","https://openalex.org/W2061779556","https://openalex.org/W2097560795","https://openalex.org/W2109087940","https://openalex.org/W2120392299","https://openalex.org/W2123184444","https://openalex.org/W2144546432","https://openalex.org/W2154597023","https://openalex.org/W2160642395","https://openalex.org/W2163947402","https://openalex.org/W3143713518","https://openalex.org/W4291316917","https://openalex.org/W6651927941","https://openalex.org/W6666114916"],"related_works":["https://openalex.org/W2114959296","https://openalex.org/W38346124","https://openalex.org/W2502442966","https://openalex.org/W2138666621","https://openalex.org/W2383936314","https://openalex.org/W1992771654","https://openalex.org/W2022661278","https://openalex.org/W2777914781","https://openalex.org/W4246369972","https://openalex.org/W4244869112"],"abstract_inverted_index":{"A":[0],"reconfigurable":[1,62],"on-die":[2],"Traffic":[3,43,107],"Generator":[4,44],"(TG)":[5],"is":[6,28,126,137,146],"proposed":[7],"to":[8,51,75,79,82,89],"test":[9],"the":[10,80,91,100,106,113,156],"packet":[11],"switched":[12],"2D-mesh":[13],"network":[14,81],"of":[15,41,61,105,123,128,139,155],"a":[16,42,120],"48":[17],"iA-32":[18],"core":[19],"Single-chip":[20,24],"Cloud":[21,25],"Computer.":[22],"The":[23,36,142],"Computer":[26],"(SCC)":[27],"an":[29],"experimental":[30],"processor":[31],"created":[32],"by":[33],"Intel":[34],"Labs.":[35],"24-tile":[37],"Network-on-Chip":[38],"(NoC)":[39],"consists":[40,60],"per":[45],"tile":[46,129,140],"which":[47,125,136],"can":[48],"be":[49],"programmed":[50],"generate":[52],"deterministic":[53],"and":[54,67,71,88,102,112,132,151],"random":[55],"traffic":[56,78],"patterns.":[57],"It":[58],"also":[59],"activity":[63],"control,":[64],"(non)-cacheable":[65],"reads":[66],"writes,":[68],"message":[69],"class":[70],"route":[72],"control":[73],"bits":[74],"feed":[76],"synthetic":[77],"investigate":[83],"NoC":[84],"functional,":[85],"protocol":[86],"issues":[87],"measure":[90],"key":[92],"power-performance":[93],"metrics.":[94],"In":[95],"this":[96],"paper,":[97],"we":[98],"present":[99],"architecture":[101],"design":[103,118],"details":[104],"Generator,":[108],"operating":[109],"modes,":[110],"re-configurability":[111],"testing":[114],"procedures.":[115],"This":[116],"semi-custom":[117],"has":[119],"transistor":[121,130],"count":[122],"54K,":[124],"0.1%":[127],"count,":[131],"occupies":[133],"0.3mm2":[134],"area":[135],"0.9%":[138],"area.":[141],"estimated":[143],"power":[144,159],"consumption":[145],"only":[147],"23mW":[148],"at":[149,152],"1.1V":[150],"500C,":[153],"0.02%":[154],"total":[157],"chip":[158],"in":[160],"45nm":[161],"high-K":[162],"nine":[163],"metal":[164],"CMOS":[165],"process.":[166]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
