{"id":"https://openalex.org/W3048487829","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9163007","title":"Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS","display_name":"Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3048487829","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9163007","mag":"3048487829"},"language":"en","primary_location":{"id":"doi:10.1109/vlsicircuits18222.2020.9163007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9163007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Steven Hsu","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090014947","display_name":"Simeon Realov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Simeon Realov","raw_affiliation_strings":["ADL, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"ADL, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Anders","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090166397","display_name":"Gregory Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory Chen","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061466560","display_name":"Monodeep Kar","orcid":"https://orcid.org/0000-0002-9318-6793"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Monodeep Kar","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074467331","display_name":"Raghavan Kumar","orcid":"https://orcid.org/0000-0001-7399-1886"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raghavan Kumar","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003823095","display_name":"H. Ekin Sumbul","orcid":"https://orcid.org/0000-0001-6812-8033"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Huseyin Sumbul","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030456056","display_name":"Phil Knag","orcid":"https://orcid.org/0000-0001-6794-8806"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phil Knag","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070239387","display_name":"Himanshu Kaul","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078003656","display_name":"Vikram Suresh","orcid":"https://orcid.org/0000-0001-8879-1967"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vikram Suresh","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu Mathew","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021268523","display_name":"Iqbal Rajwani","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Iqbal Rajwani","raw_affiliation_strings":["VTT, Intel Corp., Folsom, CA"],"affiliations":[{"raw_affiliation_string":"VTT, Intel Corp., Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013933634","display_name":"Satish Damaraju","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Damaraju","raw_affiliation_strings":["VTT, Intel Corp., Folsom, CA"],"affiliations":[{"raw_affiliation_string":"VTT, Intel Corp., Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Krishnamurthy","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Circuit Research Lab, Intel Corp., Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":16,"corresponding_author_ids":["https://openalex.org/A5109340111"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2055,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.50752298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7683294415473938},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6066604852676392},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.6056824326515198},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.599227249622345},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5744954943656921},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5590968132019043},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.521851658821106},{"id":"https://openalex.org/keywords/digital-clock","display_name":"Digital clock","score":0.5078056454658508},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.48175978660583496},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46667516231536865},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4434436559677124},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4413943588733673},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4363257884979248},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4233083426952362},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4136580228805542},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4120384156703949},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.40457338094711304},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3679114580154419},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2898908853530884},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23347198963165283},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.22328445315361023},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.20685946941375732},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.17837917804718018},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06928279995918274},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.06664595007896423}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7683294415473938},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6066604852676392},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.6056824326515198},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.599227249622345},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5744954943656921},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5590968132019043},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.521851658821106},{"id":"https://openalex.org/C2778426721","wikidata":"https://www.wikidata.org/wiki/Q1225105","display_name":"Digital clock","level":3,"score":0.5078056454658508},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.48175978660583496},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46667516231536865},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4434436559677124},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4413943588733673},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4363257884979248},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4233083426952362},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4136580228805542},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4120384156703949},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40457338094711304},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3679114580154419},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2898908853530884},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23347198963165283},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.22328445315361023},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.20685946941375732},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.17837917804718018},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06928279995918274},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.06664595007896423},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsicircuits18222.2020.9163007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9163007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2495024767","https://openalex.org/W2337711143","https://openalex.org/W2474747038","https://openalex.org/W2366663502","https://openalex.org/W2907573123","https://openalex.org/W2110902574","https://openalex.org/W2157082940","https://openalex.org/W4366088550","https://openalex.org/W2384600254","https://openalex.org/W3013924136"],"abstract_inverted_index":{"Low-clock-power":[0],"digital":[1],"standard":[2],"cell":[3],"IPs":[4,97],"in":[5,99],"10nm":[6],"CMOS,":[7],"featuring":[8],"low-power":[9],"shared-clock":[10],"(LPSC)":[11],"flip-flops":[12],"(FFs),":[13],"LPSC":[14,55],"back-to-back":[15],"(B2B)":[16],"FFs,":[17],"and":[18,30,50],"pass-gate":[19],"(PG)":[20],"integrated":[21],"clock":[22,33,103],"gates":[23],"(ICGs),":[24],"achieve":[25],"up":[26],"to":[27,80],"14%,":[28],"45%,":[29],"14%":[31],"measured":[32,83],"energy":[34],"improvements,":[35],"respectively,":[36],"by":[37],"reducing":[38],"the":[39,67],"number":[40],"of":[41,64,77,89],"clocked":[42],"devices":[43],"over":[44],"state-of-the-art":[45],"conventional":[46,81],"transmission-gate":[47],"(TG)":[48],"FF":[49,56],"AND":[51],"ICG":[52,69],"circuits.":[53],"The":[54],"achieves":[57,70],"a":[58,71,90],"mean":[59,72],"worst-case":[60],"black-hole-time":[61],"(BHT)":[62],"improvement":[63,76],"17ps,":[65],"while":[66],"PG":[68],"enable/disable":[73],"setup":[74],"time":[75],"16ps/15ps,":[78],"compared":[79],"circuits":[82],"at":[84],"650mV,":[85],"25\u00b0C.":[86],"Power":[87],"analysis":[88],"graphics":[91],"processor":[92],"block":[93],"with":[94],"these":[95],"optimized":[96],"results":[98],"an":[100],"overall":[101],"6%":[102],"power":[104],"reduction":[105],"without":[106],"frequency":[107],"impact.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
